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| Dat a She et , DS 1, Se p. 20 00 SEROCCO-M 2 Channel Serial Optimized Communication Controller PEB 20532 Version 1.2 PEF 20532 Version 1.2 Datacom Never stop thinking. Edition 2000-09-14 Published by Infineon Technologies AG, St.-Martin-Strasse 53, D-81541 Munchen, Germany (c) Infineon Technologies AG 9/14/00. All Rights Reserved. Attention please! The information herein is given to describe certain components and shall not be considered as warranted characteristics. Terms of delivery and rights to technical change reserved. We hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding circuits, descriptions and charts stated herein. Infineon Technologies is an approved CECC manufacturer. Information For further information on technology, delivery terms and conditions and prices please contact your nearest Infineon Technologies Office in Germany or our Infineon Technologies Representatives worldwide (see address list). Warnings Due to technical requirements components may contain dangerous substances. For information on the types in question please contact your nearest Infineon Technologies Office. Infineon Technologies Components may only be used in life-support devices or systems with the express written approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system, or to affect the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may be endangered. Dat a She et , DS 1, Se p. 20 00 SEROCCO-M 2 Channel Serial Optimized Communication Controller PEB 20532 Version 1.2 PEF 20532 Version 1.2 Datacom Never stop thinking. PEB 20532 Revision History: Previous Version: Page (previous Version) 32-34 80 214, 222 n.a. n.a. 253 Page (current Version) 35-37 83 218, 226 263, 266 263 257 2000-09-14 Subjects (major changes since last revision) DS 1 SEROCCO V1.1 Preliminary Data Sheet, 08.99, DS1 Correction: signal 'OSR' is multiplexed with signal 'CD', signal 'OST' is multiplexed with 'CTS' (was vice versa) corrected HDLC receive address recognition table Corrected location of TCD interrupt (async/bisync modes only) in registers ISR0 and IMR0 from bit 7 to bit 2. Added timing diagram for external DMA support signals Added address timing diagram for Intel multiplexed mode (signal ALE) Chapter "Electrical Characteristics" updated with final characterization results. For questions on technology, delivery and prices please contact the Infineon Technologies Offices in Germany or the Infineon Technologies Companies and Representatives worldwide: see our webpage at http://www.infineon.com PEB 20532 PEF 20532 Table of Contents 1 1.1 1.2 1.3 1.3.1 1.3.2 1.4 1.4.1 1.4.2 2 2.1 2.2 Page 17 18 21 22 22 24 26 26 26 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Typical Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . System Integration Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Serial Configuration Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Differences between SEROCCO-M and the ESCC Family . . . . . . . . . . . . Enhancements to the ESCC Serial Core . . . . . . . . . . . . . . . . . . . . . . . . Simplifications to the ESCC Serial Core . . . . . . . . . . . . . . . . . . . . . . . . Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Pin Diagram P-TQFP-100-3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Pin Definitions and Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 41 41 42 42 42 43 43 45 46 50 51 52 53 54 55 62 65 66 67 67 70 71 71 71 72 73 73 73 74 3 Functional Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.1 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.2 Serial Communication Controller (SCC) . . . . . . . . . . . . . . . . . . . . . . . . . . 3.2.1 Protocol Modes Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.2.2 SCC FIFOs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.2.2.1 SCC Transmit FIFO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.2.2.2 SCC Receive FIFO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.2.2.3 SCC FIFO Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.2.3 Clocking System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.2.3.1 Clock Mode 0 (0a/0b) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.2.3.2 Clock Mode 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.2.3.3 Clock Mode 2 (2a/2b) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.2.3.4 Clock Mode 3 (3a/3b) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.2.3.5 Clock Mode 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.2.3.6 Clock Mode 5a (Time Slot Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.2.3.7 Clock Mode 5b (Octet Sync Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . 3.2.3.8 Clock Mode 6 (6a/6b) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.2.3.9 Clock Mode 7 (7a/7b) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.2.4 Baud Rate Generator (BRG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.2.5 Clock Recovery (DPLL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.2.6 SCC Timer Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.2.7 SCC Serial Bus Configuration Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.2.8 Serial Bus Access Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.2.9 Serial Bus Collisions and Recovery . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.2.10 Serial Bus Access Priority Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.2.11 Serial Bus Configuration Timing Modes . . . . . . . . . . . . . . . . . . . . . . . . 3.2.12 Functions Of Signal RTS in HDLC Mode . . . . . . . . . . . . . . . . . . . . . . . . 3.2.13 Data Encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.2.13.1 NRZ and NRZI Encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Data Sheet 5 2000-09-14 PEB 20532 PEF 20532 Table of Contents 3.2.13.2 3.2.13.3 3.2.14 3.2.14.1 3.2.14.2 3.2.15 3.3 3.4 3.5 3.6 3.6.1 3.6.2 4 4.1 4.1.1 4.1.1.1 4.1.1.2 4.1.1.3 4.1.1.4 4.1.2 4.1.3 4.1.4 4.1.5 4.1.6 4.1.7 4.1.8 4.1.9 4.2 4.2.1 4.2.2 4.2.3 4.2.4 4.3 4.4 4.4.1 4.4.2 4.4.2.1 4.4.2.2 4.4.2.3 4.4.3 4.4.4 4.4.4.1 Page 74 75 76 76 77 77 78 79 80 81 81 81 82 83 83 83 84 84 85 85 87 87 89 89 89 90 90 91 91 91 92 92 95 95 95 96 96 96 97 97 98 98 FM0 and FM1 Encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Manchester Encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Modem Control Signals (RTS, CTS, CD) . . . . . . . . . . . . . . . . . . . . . . . RTS/CTS Handshaking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Carrier Detect (CD) Receiver Control . . . . . . . . . . . . . . . . . . . . . . . . Local Loop Test Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Microprocessor Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . External DMA Controller Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Interrupt Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . General Purpose Port Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GPP Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GPP Interrupt Indication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Detailed Protocol Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . HDLC/SDLC Protocol Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . HDLC Submodes Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Automode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Address Mode 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Address Mode 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Address Mode 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . HDLC Receive Data Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Receive Address Handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . HDLC Transmit Data Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Shared Flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . One Bit Insertion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Preamble Transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CRC Generation and Checking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Receive Length Check Feature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Point-to-Point Protocol (PPP) Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . Bit Synchronous PPP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Octet Synchronous PPP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Asynchronous PPP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Data Transparency in PPP Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Extended Transparent Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Asynchronous (ASYNC) Protocol Mode . . . . . . . . . . . . . . . . . . . . . . . . . . Character Framing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Data Reception . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Asynchronous Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Isochronous Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Storage of Receive Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Data Transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Special Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Break Detection/Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Data Sheet 2000-09-14 PEB 20532 PEF 20532 Table of Contents 4.4.4.2 4.4.4.3 4.5 4.5.1 4.5.2 4.5.3 4.5.4 4.5.4.1 4.6 4.6.1 4.6.2 4.6.3 5 5.1 5.2 5.2.1 5.2.2 5.2.3 5.2.4 6 6.1 6.2 6.2.1 6.2.2 6.3 6.3.1 6.3.2 7 7.1 7.2 7.3 7.4 7.5 7.6 7.7 7.7.1 7.7.1.1 7.7.1.2 7.7.1.3 7.7.2 7.7.2.1 Page In-band Flow Control by XON/XOFF Characters . . . . . . . . . . . . . . . . 98 Out-of-band Flow Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 BISYNC Protocol Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 Character Framing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 Data Reception . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 Data Transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 Special Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 Preamble Transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 Procedural Support (Layer-2 Functions) . . . . . . . . . . . . . . . . . . . . . . . . . 105 Full-Duplex LAPB/LAPD Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 Half-Duplex SDLC-NRM Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 Signaling System #7 (SS7) Operation . . . . . . . . . . . . . . . . . . . . . . . . . 113 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Register Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Detailed Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Global Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Channel Specific SCC Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Channel Specific DMA Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Miscellaneous Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Interrupt Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Data Transmission (Interrupt Driven) . . . . . . . . . . . . . . . . . . . . . . . . . . Data Reception (Interrupt Driven) . . . . . . . . . . . . . . . . . . . . . . . . . . . . External DMA Supported Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Data Transmission (With External DMA Support) . . . . . . . . . . . . . . . . Data Reception (With External DMA Support) . . . . . . . . . . . . . . . . . . . Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Operating Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Capacitances . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Thermal Package Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Microprocessor Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Microprocessor Interface Clock Timing . . . . . . . . . . . . . . . . . . . . . . Infineon/Intel Bus Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . Motorola Bus Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PCM Serial Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Clock Input Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 116 116 121 121 138 235 242 245 245 245 245 247 250 250 253 257 257 257 258 259 259 260 261 261 261 262 265 268 268 Data Sheet 2000-09-14 PEB 20532 PEF 20532 Table of Contents 7.7.2.2 7.7.2.3 7.7.2.4 7.7.2.5 7.7.2.6 7.7.3 7.7.4 8 8.1 9 Page 269 270 272 273 274 275 276 Receive Cycle Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Transmit Cycle Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Clock Mode 1 Strobe Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Clock Mode 4 Gating Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Clock Mode 5 Frame Synchronisation Timing . . . . . . . . . . . . . . . . . Reset Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . JTAG-Boundary Scan Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Test Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 277 JTAG Boundary Scan Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 277 Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 282 Data Sheet 8 2000-09-14 PEB 20532 PEF 20532 List of Figures Figure 1 Figure 2 Figure 3 Figure 4 Figure 5 Figure 6 Figure 7 Figure 8 Figure 9 Figure 10 Figure 11 Figure 12 Figure 13 Figure 14 Figure 15 Figure 16 Figure 17 Figure 18 Figure 19 Figure 20 Figure 21 Figure 22 Figure 23 Figure 24 Figure 25 Figure 26 Figure 27 Figure 28 Figure 29 Figure 30 Figure 31 Figure 32 Figure 33 Figure 34 Figure 35 Figure 36 Figure 37 Figure 38 Figure 39 Figure 40 Figure 41 Figure 42 Data Sheet Page 21 22 23 24 25 25 27 41 43 44 45 45 49 50 51 52 53 54 56 58 59 60 61 63 64 65 66 69 69 70 73 74 75 75 77 78 80 85 85 86 86 86 Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . System Integration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . System Integration With External DMA Controller . . . . . . . . . . . . . . . . Point-to-Point Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Point-to-Multipoint Bus Configuration . . . . . . . . . . . . . . . . . . . . . . . . . Multimaster Bus Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pin Configuration P-TQFP-100-3 Package . . . . . . . . . . . . . . . . . . . . . Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SCC Transmit FIFO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SCC Receive FIFO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XFIFO/RFIFO Word Access (Intel Mode) . . . . . . . . . . . . . . . . . . . . . . XFIFO/RFIFO Word Access (Motorola Mode) . . . . . . . . . . . . . . . . . . . Clock Supply Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Clock Mode 0a/0b Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Clock Mode 1 Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Clock Mode 2a/2b Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Clock Mode 3a/3b Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Clock Mode 4 Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Selecting one time-slot of programmable delay and width . . . . . . . . . Selecting one or more time-slots of 8-bit width . . . . . . . . . . . . . . . . . . Clock Mode 5a Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Clock Mode 5a "Continuous Mode" . . . . . . . . . . . . . . . . . . . . . . . . . . . Clock Mode 5a "Non Continuous Mode" . . . . . . . . . . . . . . . . . . . . . . . Selecting one or more octet wide time-slots . . . . . . . . . . . . . . . . . . . . Clock Mode 5b Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Clock Mode 6a/6b Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Clock Mode 7a/7b Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DPLL Algorithm (NRZ and NRZI Encoding, Phase Shift Enabled) . . . DPLL Algorithm (NRZ and NRZI Encoding, Phase Shift Disabled) . . . DPLL Algorithm for FM0, FM1 and Manchester Encoding . . . . . . . . . Request-to-Send in Bus Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . NRZ and NRZI Data Encoding. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . FM0 and FM1 Data Encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Manchester Data Encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . RTS/CTS Handshaking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SCC Test Loop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Interrupt Status Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . HDLC Receive Data Processing in 16 bit Automode . . . . . . . . . . . . . . HDLC Receive Data Processing in 8 bit Automode . . . . . . . . . . . . . . . HDLC Receive Data Processing in Address Mode 2 (16 bit). . . . . . . . HDLC Receive Data Processing in Address Mode 2 (8 bit). . . . . . . . . HDLC Receive Data Processing in Address Mode 1 . . . . . . . . . . . . . . 9 2000-09-14 PEB 20532 PEF 20532 List of Figures Figure 43 Figure 44 Figure 45 Figure 46 Figure 47 Figure 48 Figure 49 Figure 50 Figure 51 Figure 52 Figure 53 Figure 54 Figure 55 Figure 56 Figure 57 Figure 58 Figure 59 Figure 60 Figure 61 Figure 62 Figure 63 Figure 64 Figure 65 Figure 66 Figure 67 Figure 68 Figure 69 Figure 70 Figure 71 Figure 72 Figure 73 Figure 74 Figure 75 Figure 76 Figure 77 Figure 78 Figure 79 Figure 80 Figure 81 Figure 82 Figure 83 Page HDLC Receive Data Processing in Address Mode 0 . . . . . . . . . . . . . . 87 SCC Transmit Data Flow (HDLC Modes) . . . . . . . . . . . . . . . . . . . . . . 88 PPP Mapping/Unmapping Example. . . . . . . . . . . . . . . . . . . . . . . . . . . 94 Asynchronous Character Frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 Out-of-Band DTE-DTE Bi-directional Flow Control . . . . . . . . . . . . . . 101 Out-of-Band DTE-DCE Bi-directional Flow Control . . . . . . . . . . . . . . 102 BISYNC Message Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 Processing of Received Frames in Auto Mode . . . . . . . . . . . . . . . . . 107 Timer Procedure/Poll Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 Transmission/Reception of I-Frames and Flow Control . . . . . . . . . . . 110 Flow Control: Reception of S-Commands and Protocol Errors . . . . . 110 No Data to Send: Data Reception/Transmission . . . . . . . . . . . . . . . . 113 Data Transmission (without error), Data Transmission (with error) . . 113 Interrupt Driven Data Transmission (Flow Diagram) . . . . . . . . . . . . . 247 Interrupt Driven Data Reception (Flow Diagram) . . . . . . . . . . . . . . . . 249 DMA Transmit (Single Buffer per Packet) . . . . . . . . . . . . . . . . . . . . . 251 Fragmented DMA Transmission (Multiple Buffers per Packet) . . . . . 252 DMA Receive (Single Buffer per Packet) . . . . . . . . . . . . . . . . . . . . . . 254 Fragmented Reception per DMA (Example) . . . . . . . . . . . . . . . . . . . 255 Fragmented Reception Sequence (Example) . . . . . . . . . . . . . . . . . . 256 Input/Output Waveform for AC Tests . . . . . . . . . . . . . . . . . . . . . . . . . 259 Microprocessor Interface Clock Timing . . . . . . . . . . . . . . . . . . . . . . . 261 Infineon/Intel Read Cycle Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . 262 Infineon/Intel Write Cycle Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . 262 Infineon/Intel DMA Read Cycle Timing . . . . . . . . . . . . . . . . . . . . . . . 263 Infineon/Intel DMA Write Cycle Timing . . . . . . . . . . . . . . . . . . . . . . . 263 Infineon/Intel Multiplexed Address Timing . . . . . . . . . . . . . . . . . . . . . 263 Motorola Read Cycle Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 265 Motorola Write Cycle Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 265 Motorola DMA Read Cycle Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . 266 Motorola DMA Write Cycle Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . 266 Clock Input Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 268 Receive Cycle Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 269 Transmit Cycle Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 270 Clock Mode 1 Strobe Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 272 Clock Mode 4 Receive Gating Timing . . . . . . . . . . . . . . . . . . . . . . . . 273 Clock Mode 4 Transmit Gating Timing. . . . . . . . . . . . . . . . . . . . . . . . 273 Clock Mode 5 Frame Synchronisation Timing . . . . . . . . . . . . . . . . . . 274 Reset Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 275 JTAG-Boundary Scan Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 276 Block Diagram of Test Access Port and Boundary Scan Unit . . . . . . 277 Data Sheet 10 2000-09-14 PEB 20532 PEF 20532 List of Tables Table 1 Table 2 Table 3 Table 4 Table 5 Table 6 Table 7 Table 8 Table 9 Table 10 Table 11 Table 12 Table 13 Table 14 Table 15 Table 16 Table 17 Table 18 Table 19 Table 20 Table 21 Table 22 Table 23 Table 24 Table 25 Table 26 Table 27 Table 28 Table 29 Table 30 Table 31 Table 32 Page Microprocessor Bus Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 External DMA Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Serial Port Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 General Purpose Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Test Interface Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Power Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Overview of Clock Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 Clock Modes of the SCCs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 BRRL/BRRH Register and Bit-Fields . . . . . . . . . . . . . . . . . . . . . . . . . . 67 Data Bus Access 16-bit Intel Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 Data Bus Access 16-bit Motorola Mode. . . . . . . . . . . . . . . . . . . . . . . . 79 Protocol Mode Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 Address Comparison Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 Error Handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 Register Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 Status Information after RME interupt . . . . . . . . . . . . . . . . . . . . . . . . 248 DMA Terminology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250 Capacitances TA = 25 xC; VDD3 = 3.3 V 0.3 V, VSS = 0 V . . . . . . . . . . . . . . . . . 259 Thermal Package Characteristics P-TQFP-100-3 . . . . . . . . . . . . . . . 260 Microprocessor Interface Clock Timing . . . . . . . . . . . . . . . . . . . . . . . 261 Infineon/Intel Bus Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . 264 Motorola Bus Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 266 Clock Input Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 268 Receive Cycle Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 269 Transmit Cycle Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 271 Clock Mode 1 Strobe Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 272 Clock Mode 4 Gating Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 273 Clock Mode 5 Frame Synchronisation Timing . . . . . . . . . . . . . . . . . . 274 Reset Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 275 JTAG-Boundary Scan Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 276 Boundary Scan Sequence of SEROCCO-M . . . . . . . . . . . . . . . . . . . 278 Boundary Scan Test Modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 281 Data Sheet 11 2000-09-14 PEB 20532 PEF 20532 List of Registers Register 1 Register 2 Register 3 Register 4 Register 5 Register 6 Register 7 Register 8 Register 9 Register 10 Register 11 Register 12 Register 13 Register 14 Register 15 Register 16 Register 17 Register 18 Register 19 Register 20 Register 21 Register 22 Register 23 Register 24 Register 25 Register 26 Register 27 Register 28 Register 29 Register 30 Register 31 Register 32 Register 33 Register 34 Register 35 Register 36 Register 37 Register 38 Register 39 Register 40 Register 41 Register 42 Data Sheet Page GCMDR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GMODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GSTAR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GPDIRL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GPDIRH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GPDATL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GPDATH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GPIML . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GPIMH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GPISL. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GPISH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DCMDR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DISR. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DIMR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . FIFOL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . FIFOH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . STARL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . STARH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CMDRL. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CMDRH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CCR0L . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CCR0H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CCR1L . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CCR1H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CCR2L . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CCR2H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CCR3L . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CCR3H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PREAMB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TOLEN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ACCM0. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ACCM1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ACCM2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ACCM3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . UDAC0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . UDAC1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . UDAC2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . UDAC3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TTSA0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TTSA1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TTSA2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TTSA3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 121 122 124 126 126 128 128 130 130 132 132 134 135 137 138 138 141 141 146 146 151 151 155 155 160 160 167 167 175 176 177 177 178 178 180 180 181 181 183 183 184 184 2000-09-14 PEB 20532 PEF 20532 List of Registers Register 43 Register 44 Register 45 Register 46 Register 47 Register 48 Register 49 Register 50 Register 51 Register 52 Register 53 Register 54 Register 55 Register 56 Register 57 Register 58 Register 59 Register 60 Register 61 Register 62 Register 63 Register 64 Register 65 Register 66 Register 67 Register 68 Register 69 Register 70 Register 71 Register 72 Register 73 Register 74 Register 75 Register 76 Register 77 Register 78 Register 79 Register 80 Register 81 Register 82 Register 83 Register 84 Data Sheet Page RTSA0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . RTSA1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . RTSA2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . RTSA3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PCMTX0. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PCMTX1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PCMTX2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PCMTX3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PCMRX0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PCMRX1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PCMRX2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PCMRX3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . BRRL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . BRRH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TIMR0. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TIMR1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TIMR2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TIMR3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XAD1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XAD2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . RAL1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . RAH1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . RAL2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . RAH2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . AMRAL1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . AMRAH1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . AMRAL2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . AMRAH2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . RLCRL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . RLCRH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XOFF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MXON. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MXOFF. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TCR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TICR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ISR0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ISR1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ISR2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IMR0. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IMR1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IMR2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 186 186 187 187 189 189 190 190 192 192 193 193 195 195 197 197 198 198 201 201 203 203 204 204 206 206 207 207 209 209 211 211 213 213 215 216 218 218 219 226 226 227 2000-09-14 PEB 20532 PEF 20532 List of Registers Register 85 Register 86 Register 87 Register 88 Register 89 Register 90 Register 91 Register 92 Register 93 Register 94 Register 95 Register 96 Register 97 Page RSTA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SYNCL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SYNCH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XBCL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XBCH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . RMBSL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . RMBSH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . RBCL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . RBCH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VER0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VER1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VER2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VER3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229 233 233 236 236 238 238 240 240 242 242 243 243 Data Sheet 14 2000-09-14 PEB 20532 PEF 20532 Preface The 2 Channel Serial Optimized Communication Controller PEB 20532 (SEROCCO-M) is a Protocol Controller for a wide range of data communication and telecommunication applications. This document provides complete reference information on hardware and software related issues as well as on general operation. Organization of this Document This Data Sheet is divided into 9 chapters. It is organized as follows: * Chapter 1, Introduction Gives a general description of the product, lists the key features, and presents some typical applications. * Chapter 2, Pin Descriptions Lists pin locations with associated signals, categorizes signals according to function, and describes signals. * Chapter 3, Functional Overview This chapter provides detailed descriptions of all SEROCCO-M internal functional blocks. * Chapter 4, Detailed Protocol Description Gives a detailed description of all protocols supported by the serial communication controllers SCCs. * Chapter 5, Register Description Gives a detailed description of all SEROCCO-M on chip registers. * Chapter 6, Programming Provides programming help for SEROCCO-M initialization procedure and operation. * Chapter 7, Electrical Characteristics Gives a detailed description of all electrical DC and AC characteristics and provides timing diagrams and values for all interfaces. * Chapter 8, Test Modes Gives a detailed description of the JTAG boundary scan unit. * Chapter 9, Package Outlines Data Sheet 15 2000-09-14 PEB 20532 PEF 20532 Your Comments We welcome your comments on this document. We are continuously trying improving our documentation. Please send your remarks and suggestions by e-mail to sc.docu_comments@infineon.com Please provide in the subject of your e-mail: device name (SEROCCO-M), device number (PEB 20532, PEF 20532), device version (Version 1.2), and in the body of your e-mail: document type (Data Sheet), issue date (2000-09-14) and document revision number (DS 1). Data Sheet 16 2000-09-14 PEB 20532 PEF 20532 Introduction 1 Introduction The SEROCCO-M is a Serial Communication Controller with two independent serial channels1). The serial channels are derived from updated protocol logic of the ESCC and DSCC4 device family providing a large set of protocol support and variety in serial interface configuration. This allows easy integration to different environments and applications. A generic 8- or 16-bit multiplexed/demultiplexed slave interface provides fast device access with low bus utilization and easy software handshaking. DMA handshake control signals allow connection to an external DMA controller. Large on-chip FIFOs of 64 byte capacity per port and direction in combination with enhanced threshold control mechanisms allow decoupling of traffic requirements on host bus and serial interfaces with little exception probabilities such as data underruns or overflows. Each of the two Serial Communication Controllers (SCC) contains an independent Baud Rate Generator, DPLL and programmable protocol processing (HDLC, PPP, ASYNC and BISYNC). Data rates of up to 16 Mbit/s (HDLC, PPP, bit transparent) and 2 Mbit/s (DPLL assisted modes) are supported. The channels can also handle a large set of layer-2 protocol functions (LAPD, SS7) reducing bus and host CPU load. Two channel specific timers are provided to support protocol functions. 1) The serial channels are also called 'ports' or 'cores' depending on the context. Data Sheet 17 2000-09-14 2 Channel Serial Optimized Communication Controller SEROCCO-M PEB 20532 PEF 20532 Version 1.2 CMOS 1.1 Features Serial communication controllers (SCCs) * Two independent channels * Full duplex data rates on each channel of up to 16 Mbit/s sync - 2 Mbit/s with DPLL * 64 Bytes deep receive FIFO per SCC * 64 Bytes deep transmit FIFO per SCC Serial Interface On-chip clock generation or external clock sources On-chip DPLLs for clock recovery Baud rate generator Clock gating signals Clock gapping capability Programmable time-slot capability for connection to TDM interfaces (e.g. T1, E1) * NRZ, NRZI, FM and Manchester data encoding * Optional data flow control using modem control lines (RTS, CTS, CD) * Support of bus configuration by collision detection and resolution Bit Processor Functions * HDLC/SDLC Protocol Modes - Automatic flag detection and transmission - Shared opening and closing flag - Generation of interframe-time fill '1's or flags - Detection of receive line status - Zero bit insertion and deletion * * * * * * P-TQFP-100-3 P-TQFP-128-1 Type PEB 20532, PEF 20532 Package P-TQFP-100-3 Data Sheet 1-18 2000-09-14 PEB 20532 PEF 20532 Introduction - CRC generation and checking (CRC-CCITT or CRC-32) - Transparent CRC option per channel and/or per frame - Programmable Preamble (8 bit) with selectable repetition rate - Error detection (abort, long frame, CRC error, short frames) Bit Synchronous PPP Mode - Bit oriented transmission of HDLC frame (flag, data, CRC, flag) - Zero bit insertion/deletion - 15 consecutive '1' bits abort sequence Octet Synchronous PPP Mode - Octet oriented transmission of HDLC frame (flag, data, CRC, flag) - Programmable character map of 32 hard-wired characters (00H-1FH) - Four programmable characters for additional mapping - Insertion/deletion of control-escape character (7DH) for mapped characters Asynchronous PPP Mode - Character oriented transmission of HDLC frame (flag, data, CRC, flag) - Start/stop bit framing of single character - Programmable character map of 32 hard-wired characters (00H-1FH) - Four programmable characters for additional mapping - Insertion/deletion of control-escape character (7DH) for mapped characters Asynchronous (ASYNC) Protocol Mode - Selectable character length (5 to 8 bits) - Even, odd, forced or no parity generation/checking - 1 or 2 stop bits - Break detection/generation - In-band flow control by XON/XOFF - Immediate character insertion - Termination character detection for end of block identification - Time out detection - Error detection (parity error, framing error) BISYNC Protocol Mode - Programmable 6/8 bit SYN pattern (MONOSYNC) - Programmable 12/16 bit SYN pattern (BISYNC) - Selectable character length (5 to 8 bits) - Even, odd, forced or no parity generation/checking - Generation of interframe-time fill '1's or SYN characters - CRC generation (CRC-16 or CRC-CCITT) - Transparent CRC option per channel and/or per frame - Programmable Preamble (8 bit) with selectable repetition rate - Termination character detection for end of block identification - Error detection (parity error, framing error) Extended Transparent Mode - Fully bit transparent (no framing, no bit manipulation) - Octet-aligned transmission and reception 19 2000-09-14 * * * * * * Data Sheet PEB 20532 PEF 20532 Introduction * Protocol and Mode Independent - Data bit inversion - Data overflow and underrun detection - Timer Protocol Support * Address Recognition Modes - No address recognition (Address Mode 0) - 8-bit (high byte) address recognition (Address Mode 1) - 8-bit (low byte) or 16-bit (high and low byte) address recognition (Address Mode 2) * HDLC Automode - 8-bit or 16-bit address generation/recognition - Support of LAPB/LAPD - Automatic handling of S- and I-frames - Automatic processing of control byte(s) - Modulo-8 or modulo-128 operation - Programmable time-out and retry conditions - SDLC Normal Response Mode (NRM) operation for slave * Signaling System #7 (SS7) support - Detection of FISUs, MSUs and LSSUs - Unchanged Fill-In Signaling Units (FISUs) not forwarded - Automatic generation of FISUs in transmit direction (incl. sequence number) - Counting of errored signaling units * Optional DTACK/READY controlled cycles Microprocessor Interface * * * * * 8/16-bit bus interface Multiplexed and De-multiplexed address/data bus Intel/Motorola style Asynchronous interface Maskable interrupts for each channel General Purpose Port (GPP) Pins (up to 7) General * * * * 3.3V power supply with 5V tolerant inputs Low power consumption Power safe features P-TQFP-100-3 Package (Thermal Resistance: RJA = 42 K/W) Data Sheet 20 2000-09-14 PEB 20532 PEF 20532 Introduction 1.2 Logic Symbol JTAG Test Interface TCK TMS TDI TDO TRST TEST VSS VDD3 A(7:0) ALE 1) D(15:0) RD 1) WR 1) BHE 1) LDS 2) UDS 2) R/W 2) DTACK CS INT/INT CLK RESET Microprocessor Interface SEROCCO-M PEB 20532 PEF 20532 TxDA RxDA RTSA/TxCLKOA Serial CTSA/CxDA/TCGA/OSTA Channel A CDA/FSCA/RCGA/OSRA TxCLKA RxCLKA TxDB RxDB RTSB/TxCLKOB Serial CTSB/CxDB/TCGB/OSTB Channel B CDB/FSCB/RCGB/OSRB TxCLKB RxCLKB DRTA DRRA DACKA GPn 1) 2) Intel bus mode Motorola bus mode External DMA Interface DRTB DRRB DACKB General Purpose Port Figure 1 Logic Symbol Data Sheet 21 XTAL1 XTAL2 2000-09-14 PEB 20532 PEF 20532 Introduction 1.3 Typical Applications SEROCCO-M devices can be used in LAN-WAN inter-networking applications such as Routers, Switches and Trunk cards and support the common V.35, ISDN BRI (S/T) and RFC1662 standards. Its new features provide powerful hardware and software interfaces to develop high performance systems. 1.3.1 System Integration Example Transceiver, Framer ... CPU SEROCCO-M PEB 20532 PEF 20532 ... ... System Bus RAM Bank Figure 2 System Integration Data Sheet 22 ... 2000-09-14 PEB 20532 PEF 20532 Introduction Transceiver, Framer ... CPU SEROCCO-M PEB 20532 PEF 20532 ... ... System Bus RAM Bank DMA Controller Figure 3 System Integration With External DMA Controller Data Sheet 23 ... 2000-09-14 PEB 20532 PEF 20532 Introduction 1.3.2 Serial Configuration Examples SEROCCO-M supports a variety of serial configurations at Layer-1 and Layer-2 level. The outstanding variety of clock modes supporting a large number of combinations of external and internal clock sources allows easy integration in application environments. serial transmission optional modem control signals Layer-2 LAPD/B or SS7 Protocol Support ... RxD TxD RxD ... TxD SEROCCO-M PEB 20532 PEF 20532 SEROCCO-M PEB 20532 PEF 20532 ... ... ... ... Figure 4 Point-to-Point Configuration Data Sheet 24 ... ... 2000-09-14 PEB 20532 PEF 20532 Introduction ... Master SEROCCO-M PEB 20532 PEF 20532 TxD RxD ... ... Layer-1 collision detection or Layer-2 SDLC-NRM operation ... RxD CxD TxD RxD ... CxD TxD RxD Slave 1 Slave 2 SEROCCO-M PEB 20532 PEF 20532 ... ... ... Figure 5 Point-to-Multipoint Bus Configuration Layer-1 collision detection ... RxD CxD TxD RxD ... CxD TxD RxD ... CxD TxD Master 1 Master 2 Master n SEROCCO-M PEB 20532 PEF 20532 SEROCCO-M PEB 20532 PEF 20532 ... ... ... ... SEROCCO-M PEB 20532 PEF 20532 Figure 6 Multimaster Bus Configuration Data Sheet 25 ... ... ... ... ... CxD TxD Slave n SEROCCO-M PEB 20532 PEF 20532 ... ... ... ... ... ... ... ... ... 2000-09-14 ... PEB 20532 PEF 20532 Introduction 1.4 Differences between SEROCCO-M and the ESCC Family This chapter is useful for all being familiar with the ESCC family. 1.4.1 Enhancements to the ESCC Serial Core The SEROCCO-M SCC cores contain the core logic of the ESCC as the heart of the device. Some enhancements are incorporated in the SCCs. These are: * * * * * * Octet-, Bit Synchronous and Asynchronous PPP protocol support as in RFC-1662 Signaling System #7 (SS7) support 4-kByte packet length byte counter Enhanced address filtering (16-bit maskable) Enhanced time slot assigner Support of high data rates (16 Mbit/s) 1.4.2 Simplifications to the ESCC Serial Core The following features of the ESCC core have been removed: * Extended transparent mode 0 (this mode provided octet buffered data reception without usage of FIFOs; SEROCCO-M supports octet buffered reception via appropriate threshold configurations for the SCC receive FIFOs) * Support of interrupt acknowledge cycles * Master clock mode Data Sheet 26 2000-09-14 PEB 20532 PEF 20532 Pin Descriptions 2 2.1 Pin Descriptions Pin Diagram P-TQFP-100-3 (top view) P-TQFP-100-3 D11 D10 D9 D8 VSS VDD TEST2 TEST1 D7 D6 D5 D4 VSS VDD D3 D2 D1 D0 VSS VDD CLK READY#/DTACK# WR# RD# VSS 75 70 65 60 VDD VSS D12 D13 D14 D15 VDD VSS DRTA DACKA# DRRA DRRB/GP1 DRTB/GP0 DACKB#/GP2 RTSB# RxDB VDD VSS RxCLKB TxDB TxCLKB CDB/FSCB/RCGB#/OSRB VDD TRST# TDI 55 50 80 45 85 40 90 35 95 30 10 15 20 Figure 7 Pin Configuration P-TQFP-100-3 Package Data Sheet TDO TCK VDD VSS CTSB#/CxDB/TCGB#/OSTB VSSA XTAL2 XTAL1 VDDA CTSA#/CxDA/TCGA#/OSTA CDA/FSCA/RCGA#/OSRA RxDA RxCLKA TxDA VDD VSS TxCLKA RTSA# RESET# INT/INT# VDD VSS GP10 GP9 GP8 27 25 1 5 100 VSS VDD VSS VDD TMS R/W# DS#/BHE#/LDS# CS# BM/ALE VSS VDD A0/BLE#/UDS# A1 A2 A3 VDD VSS WIDTH A4 A5 A6 A7 VSS VDD GP6 2000-09-14 PEB 20532 PEF 20532 Pin Descriptions 2.2 Table 1 Pin No. Pin Definitions and Functions Microprocessor Bus Interface P-TQFP100-3 Symbol In (I) Function Out (O) D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 A7 A6 A5 A4 A3 A2 A1 I/O Data Bus The data bus lines are bi-directional tri-state lines which interface with the system's data bus. 81 80 79 78 75 74 73 72 67 66 65 64 61 60 59 58 29 30 31 32 36 37 38 I I I I I I I Address Bus These pins connect to the system's address bus to select one of the internal registers for read or write. Data Sheet 28 2000-09-14 PEB 20532 PEF 20532 Pin Descriptions Table 1 Pin No. P-TQFP100-3 Microprocessor Bus Interface Symbol In (I) Function Out (O) A0 I Address Line A0 (8-bit modes) In Motorola and in Intel 8-bit mode this signal represents the least significant address line. Byte Low Enable (16-bit Intel bus mode) This signal indicates a data transfer on the lower byte of the data bus (D7..D0). Together with signal BHE the type of bus access is determined (byte or word access at even or odd address). Upper Data Strobe (16-bit Motorola bus mode) This active low strobe signal serves to control read/write operations. Together with signal LDS the type of bus access is determined. Bus Mode - BM = static '1' for operation in Motorola bus mode (de-multiplexed). - BM = static '0' for operation in Intel bus mode with de-multiplexed address and data buses. - Pin BM/ALE has the function of an Address Latch Enable (ALE) for operation in Intel bus mode with a multiplexed address/data bus. A falling edge on this pin selects Intel multiplexed bus mode. Address Latch Enable (mux'ed Intel bus) The address is latched by the SEROCCO-M with the falling edge of ALE. The address input pins A(7:0) pins A(15:0) must be externally connected to the data bus pins D(7:0)D(15:0). For operation of the 8-bit SEROCCO-M ( package) in a 16-bit environment, A(7:0) should be connected to address/data lines AD(8:1) of the external bus. D(7:0) interface to AD(7:0) of the external bus. 39 BLE I UDS I 42 BM I ALE I Data Sheet 29 2000-09-14 PEB 20532 PEF 20532 Pin Descriptions Table 1 Pin No. P-TQFP100-3 Microprocessor Bus Interface Symbol In (I) Function Out (O) DS I Data Strobe (8-bit Motorola bus mode only) This active low strobe signal serves to control read/write operations. Bus High Enable (16-bit Intel bus mode only) This signal indicates a data transfer on the upper byte of the data bus (D15..D8). In 8-bit Intel bus mode this signal has no function. Lower Data Strobe (16-bit Motorola bus mode) This active low strobe signal serves to control read/write operations. Together with signal UDS the type of bus access is determined (byte or word access at even or odd address). In 8-bit Intel bus mode, a pull-up resistor to VDD3 is recommended on this pin. 52 RD I Read Strobe (Intel bus mode only) This signal indicates a read operation. The current bus master is able to accept data on lines D(7:0) / D(15:0) during an active RD signal. In Motorola bus mode, a pull-up resistor to VDD3 is recommended on this pin. Read/Write Enable (Motorola bus mode) This signal distinguishes between read and write operation. As an input it must be valid during data strobe (DS). In Intel bus mode, a pull-up resistor to VDD3 is recommended on this pin. Chip Select A low signal selects SEROCCO-M for read/write operations. 44 BHE I LDS I 45 R/W I 43 CS I Data Sheet 30 2000-09-14 PEB 20532 PEF 20532 Pin Descriptions Table 1 Pin No. P-TQFP100-3 Microprocessor Bus Interface Symbol In (I) Function Out (O) WR I Write Strobe (Intel bus mode only) This signal indicates a write operation. The current bus master presents valid data on lines D(7:0) / D(15:0) during an active WR signal. In Motorola bus mode, a pull-up resistor to VDD3 is recommended on this pin. Width Of Bus Interface A low signal on this input selects the 8-bit bus interface mode. A high signal on this input selects the 16-bit bus interface mode. In this case word transfer to/from the internal registers is enabled. Byte transfers are implemented by using BLE and BHE (Intel bus mode) or LDS and UDS (Motorola bus mode) Clock The system clock for SEROCCO-M is provided through this pin. Interrupt Request The INT/INT goes active when one or more of the bits in registers ISR0..ISR2 are set to '1'. A read to these registers clears the interrupt. The INT/ INT line is inactive when all interrupt status bits are reset. Interrupt sources can be unmasked in registers IMR0..IMR2 by setting the corresponding bits to '0'. Ready (Intel bus mode) Data Transfer Acknowledge (Motorola mode) During a slave access (register read/write) this signal (output) indicates, that the SEROCCO-M is ready for data transfer. The signal remains active until the data strobe (DS in Motorola bus mode, RD/WR in Intel bus mode) and/or the chip select (CS) go inactive. This line is tri-state when unused. A pull-up resistor to VDD3 is recommended if this function is not used. 31 2000-09-14 53 33 WIDTH I 55 CLK I 20 INT/INT O o/d 54 READY O DTACK O Data Sheet PEB 20532 PEF 20532 Pin Descriptions Table 1 Pin No. P-TQFP100-3 Microprocessor Bus Interface Symbol In (I) Function Out (O) RESET I Reset With this active low signal the on-chip registers and state machines are forced to reset state. During Reset all pins are in a high impedance state. 19 Table 2 Pin No. External DMA Interface P-TQFP100-3 Symbol In (I) Function Out (O) DRTA O DMA Request Transmitter Channel A The transmitter on a this channel requests a DMA transfer by activating the DRTA line. The request remains active as long as the Transmit FIFO requires data transfers. The amount of data bytes to be transferred from the system memory to the serial channel (= Byte Count) must be written first to the XBCL, XBCH registers. Always blocks of data (n x 32 bytes + rest ; n=0,1,...) are transferred till the Byte Count is reached. DRTA is deactivated with the beginning of the last write cycle. DMA Request Receiver Channel A The receiver on this serial channel requests a DMA transfer by activating the DRRA line. The request remains active as long as the Receive FIFO requires data transfers, thus always blocks of data are transferred. DRRA is deactivated immediately following the falling edge of the last read cycle. 84 86 DRRA O Data Sheet 32 2000-09-14 PEB 20532 PEF 20532 Pin Descriptions Table 2 Pin No. P-TQFP100-3 External DMA Interface Symbol In (I) Function Out (O) DACKA I DMA Acknowledge Channel A A low signal on this pin informs the SEROCCO-M that the requested DMA cycle controlled via DRTA or DRRA of this channel is in progress, i.e. the DMA controller has achieved bus mastership from the CPU and will start data transfer cycles (either write or read). In conjunction with a read or write operation this input serves as Access Enable (similar to CS) to the respective FIFOs. If DACKA is active, the input to pins A(7:0) and CS is ignored and the FIFOs are implicitly selected. If not used, a pull-up resistor to VDD is required for this pin. DMA Request Transmitter Channel B (corresponding to channel A) General Purpose Pin #0 If DMA support is not enabled, this pin serves as a general pupose input/output pin. After reset this pin serves as a general purpose input. A pull-up resistor to VDD3 is recommended. DMA Request Receiver Channel B (corresponding to channel A) General Purpose Pin #1 If DMA support is not enabled, this pin serves as a general pupose input/output pin. After reset this pin serves as a general purpose input. A pull-up resistor to VDD3 is recommended. DMA Acknowledge Channel B (corresponding to channel A) General Purpose Pin #2 If DMA support is not enabled, this pin serves as a general pupose input/output pin. A pull-up resistor to VDD3 is recommended if this pin is not used. 33 2000-09-14 85 88 DRTB O GP0 I/O 87 DRRB O GP1 I/O 89 DACKB I GP2 I/O Data Sheet PEB 20532 PEF 20532 Pin Descriptions Table 3 Pin No. Serial Port Pins P-TQFP100-3 Symbol In (I) Function Out (O) TxCLK A I/O Transmit Clock Channel A The function of this pin depends on the selected clock mode and the value of bit 'TOE' (CCR0L register, refer to Table 8 "Clock Modes of the SCCs" on Page 47). 17 If programmed as Input (CCR0L.TOE='0'), either - the transmit clock for the channel (clock mode 0a, 2a, 4, 5b, 6a), or - a transmit strobe signal for the channel (clock mode 1) can be provided to this pin. If programmed as Output (CCR0L.TOE='1'), this pin supplies either - the transmit clock from the baud rate generator (clock mode 0b, 2b, 3b, 6b, 7b), or - the transmit clock from the DPLL circuit (clock mode 3a, 7a), or - an active-low control signal marking the programmed transmit time-slot in clock mode 5a. 13 RxCLK A I Receive Clock Channel A The function of this pin depends on the selected clock mode (refer to Table 8 "Clock Modes of the SCCs" on Page 47). A signal provided on pin RxCLKA may supply - the receive clock (clock mode 0, 4, 5b), or - the receive and transmit clock (clock mode 1, 5a), or - the clock input for the baud rate generator (clock mode 2, 3). Data Sheet 34 2000-09-14 PEB 20532 PEF 20532 Pin Descriptions Table 3 Pin No. P-TQFP100-3 Serial Port Pins (cont'd) Symbol In (I) Function Out (O) CDA I Carrier Detect Channel A The function of this pin depends on the selected clock mode. It can supply - either a modem control or a general purpose input (clock modes 0, 2, 3, 6, 7). If auto-start is programmed, it functions as a receiver enable signal. - or a receive strobe signal (clock mode 1). Polarity of CDA can be set to 'active low' with bit ICD in register CCR1H. Additionally, an interrupt may be issued if a state transition occurs at the CDA pin (programmable feature). Frame Sync Clock Channel A (cm 5a) When the SCC is in the time-slot oriented clock mode 5a, this pin functions as the Frame Synchronization Clock input. Receive Clock Gating Channel A (cm 4) In clock mode 4 this pin is used as Receive Clock Gating signal. If no clock gating function is required, a pull-up resistor to VDD3 is recommended. Octet Sync Receive Channel A (cm 5b) (clock mode 5b) When the SCC is in the time-slot oriented clock mode with octet-alignment (clock mode 5b), received octets are aligned to this synchronization pulse input. 11 FSCA I RCGA I OSRA I Data Sheet 35 2000-09-14 PEB 20532 PEF 20532 Pin Descriptions Table 3 Pin No. P-TQFP100-3 Serial Port Pins (cont'd) Symbol In (I) Function Out (O) RTSA O Request to Send Channel A The function of this pin depends on the settings of bits RTS, FRTS in register CCR1H . In bus configuration, RTS can be programmed to: - go low during the actual transmission of a frame shifted by one clock period, excluding collision bits. - go low during reception of a data frame. - stay always high (RTS disabled). Clear to Send Channel A A low on the CTSA input enables the transmitter. Additionally, an interrupt may be issued if a state transition occurs at the CTSA pin (programmable feature). If no 'Clear To Send' function is required, a pulldown resistor to VSS is recommended. 18 10 CTSA I CxDA I Collision Data Channel A In a bus configuration, the external serial bus must be connected to the corresponding CxDA pin for collision detection. A collision is detected whenever a logical '1' is driven on the open drain TxDA output but a logical '0' is detected via CxDA input. Transmit Clock Gating Channel A (cm 4) In clock mode 4 these pins are used as Transmit Clock Gating signals. If no clock gating function is required, a pull-up resistor to VDD3 is recommended. Octet Sync Transmit Channel A (cm 5b) When the SCC is in the time-slot oriented clock mode with octet-alignment (clock mode 5b), a synchronization pulse on this input pin aligns transmit octets. TCGA I OSTA I Data Sheet 36 2000-09-14 PEB 20532 PEF 20532 Pin Descriptions Table 3 Pin No. P-TQFP100-3 Serial Port Pins (cont'd) Symbol In (I) Function Out (O) TxDA O o/d Transmit Data Channel A Transmit data is shifted out via this pin. It can be configured as push/pull or open drain output characteristic via bit 'ODS' in register CCR1L. Receive Data Channel A Serial data is received on this pin. Transmit Clock Channel B (corresponding to channel A) Receive Clock Channel B (corresponding to channel A) Carrier Detect Channel B Frame Sync Clock Channel B (cm 5a) Receive Clock Gating Channel B (cm 4) Octet Sync Receive Channel B (cm 5b) (corresponding to channel A) Request to Send Channel B (corresponding to channel A) Clear to Send Channel B Collision Data Channel B Transmit Clock Gating Channel B (cm 4) Octet Sync Transmit Channel B (cm 5b) (corresponding to channel A) Transmit Data Channel B (corresponding to channel A) 14 12 96 94 97 RxDA TxCLK B RxCLK B CDB FSCB RCGB OSRB RTSB CTSB CxDB TCGB OSTB TxDB I I/O I I I I I O I I I I O o/d 90 5 95 Data Sheet 37 2000-09-14 PEB 20532 PEF 20532 Pin Descriptions Table 3 Pin No. P-TQFP100-3 Serial Port Pins (cont'd) Symbol In (I) Function Out (O) RxDB XTAL1 XTAL2 I I O Receive Data Channel B (corresponding to channel A) Crystal Connection If the internal oscillator is used for clock generation (clock modes 0b, 6, 7) the external crystal has to be connected to these pins. The internal oscillator should be powered up (GMODE:OSCPD = '0') and the signal shaper may be activated (GMODE:DSHP = '0'). Moreover, XTAL1 may be used as input for a common clock source to both SCCs, provided by an external clock generator (oscillator). In this case the oscillator unit may be powered down and it is recommended to bypass the shaper of the internal oscillator unit by setting bit 'DSHP' to '1'. A pull-down resistor to VSS is recommended for pin XTAL1 if not used. 91 8 7 Table 4 Pin No. General Purpose Pins P-TQFP100-3 Symbol In (I) Function Out (O) GP10 GP9 GP8 GP6 I/O General Purpose Pins These pins serve as general purpose input/output pins. 23 24 25 26 Data Sheet 38 2000-09-14 PEB 20532 PEF 20532 Pin Descriptions Table 5 Pin No. Test Interface Pins P-TQFP100-3 Symbol In (I) Function Out (O) TRST I JTAG Reset Pin (internal pull-up) For proper device operation, a reset for the boundary scan controller must be supplied to this active low pin. If the boundary scan of the SEROCCO-M is not used, this pin can be connected to VSS to keep it in reset state. JTAG Test Clock (internal pull-up) If the boundary scan of the SEROCCO-M is not used, this pin may remain unconnected. 99 2 TCK I 100 TDI I JTAG Test Data Input (internal pull-up) If the boundary scan of the SEROCCO-M is not used, this pin may remain unconnected. JTAG Test Data Output JTAG Test Mode Select (internal pull-up) If the boundary scan of the SEROCCO-M is not used, this pin may remain unconnected. Test Input 1 When connected to VDD3 the SEROCCO-M works in a vendor specific test mode. This pin must be connected to VSS. Test Input 2 When connected to VDD3 the SEROCCO-M works in a vendor specific test mode. This pin must be connected to VSS. 1 46 TDO TMS O I 68 TEST1 I 69 TEST2 I Data Sheet 39 2000-09-14 PEB 20532 PEF 20532 Pin Descriptions Table 6 Pin No. P-TQFP100-3 Power Pins Symbol In (I) Function Out (O) - 3, 15, VDD3 21, 27, 35, 40, 47, 49, 56, 62, 70, 76, 82, 92, 98 4, 16, VSS 22, 28, 34, 41, 48, 50, 51, 57, 63, 71, 77, 83, 93 9 VDDA Digital Supply Voltage 3.3 V 0.3 V All pins must be connected to the same voltage potential. - Digital Ground (0 V) All pins must be connected to the same voltage potential. - Analog Supply Voltage 3.3 V 0.3 V This pin supplies the on-chip oscillator of the SEROCCO-M. If no separate analog power supply is available, this pin can be directly connected to VDD3. Analog Ground (0 V) This pin supplies the ground level to the on-chip oscillator of the SEROCCO-M. If no separate analog power supply is available, this pin can be directly connected to VSS. Not Connected 6 VSSA - - N.C. - Data Sheet 40 2000-09-14 PEB 20532 PEF 20532 Functional Overview 3 Functional Overview The functional blocks of SEROCCO-M can be divided into two major domains: - the microprocessor interface of SEROCCO-M provides access to on-chip registers and to the "user" portion of the receive and transmit FIFOs (RFIFO/XFIFO). Optionally these FIFOs can be accessed by an external 4-channel DMA controller. - the Serial Communication Controller (SCC) is capable of processing bit-synchronous (HDLC/SDLC/bitsync PPP) and octet-synchronous (octet-sync PPP) as well as fully transparent data traffic. Data exchange between the serial communication controller and the microprocessor interface is performed using FIFOs, decoupling these two domains. 3.1 Figure 8 Block Diagram Block Diagram 5 JTAG Test Interface Serial Channel A LAP Control Transmit Protocol Machine Receive Protocol Machine TSA Decoder/ Collision Detection DPLL 7 BRG Clock Control Transmit FIFO (32 Byte) Receive FIFO (32 Byte) M icro p ro ces s o r In terfac e Transmit FIFO (32 Byte) Receive FIFO (32 Byte) Oscillator 26 Serial Channel B Transmit FIFO (32 Byte) Receive FIFO (32 Byte) 7 External DMA Interface 6 Data Sheet 41 2000-09-14 PEB 20532 PEF 20532 Functional Overview 3.2 3.2.1 Serial Communication Controller (SCC) Protocol Modes Overview The SCC is a multi-protocol communication controller. The core logic provides different protocol modes which are listed below: * HDLC Modes - HDLC Transparent Operation (Address Mode 0) - HDLC Address Recognition (Address Mode 1, Address Mode 2 8/16-bit) - Full-Duplex LAPB/LAPD Operation (Automode 8/16-bit) - Half-Duplex SDLC-NRM Operation (Automode 8-bit) - Signaling System #7 (SS7) Operation * Point-to-Point Protocol (PPP) Modes - Bit Synchronous PPP - Octet Synchronous PPP - Asynchronous PPP * ASYNC Modes - Asynchronous Mode - Isochronous Mode * BISYNC Modes - Bisynchronous Mode - Monosynchronous Mode * Extended Transparent Mode A detailed description of these protocol modes is given in Chapter 4, starting on Page 82. 3.2.2 SCC FIFOs Each SCC provides its own transmit and receive FIFOs to handle internal arbitration and microcontroller latencies. Data Sheet 42 2000-09-14 PEB 20532 PEF 20532 Functional Overview 3.2.2.1 SCC Transmit FIFO The SCC transmit FIFO is divided into two parts of 32 bytes each ('transmit pools'). The interface between the two parts provides synchronization between the microprocessor accesses and the protocol logic working with the serial transmit clock. Microprocessor/DMA Interface 32 byte Transmit Pool (accessable by CPU) Transmit Protocol Machine 32 byte Shadow part (not accessable by CPU) Figure 9 SCC Transmit FIFO A 32 bytes FIFO part is accessable by the CPU/DMA controller; it accepts transmit data even if the SCC is in power-down condition (register CCR0H bit PU='0'). The only exception is a transmit data underrun (XDU) event. In case of an XDU event (e.g. after excessive bus latency), the FIFO will neither accept more data nor transfer another byte to the protocol logic. This XDU blocking mechanism prevents unexpected serial data. The blocking condition must be cleared by reading the interrupt status register ISR1 after the XDU interrupt was generated. Thus, the XDU interrupt indication should not be masked in register IMR1. Transfer of data to the 32 byte shadow part only takes place if the SCC is in power-up condition and an appropriate transmit clock is provided depending on the selected clock mode. Serial data transmission will start as soon as at least one byte is transferred into the shadow FIFO and transmission is enabled depending on the selected clock mode (CTS signal active, clock strobe signal active, timeslot valid or clock gapping signal inactive). 3.2.2.2 SCC Receive FIFO The SCC receive FIFO is divided into two parts of 32 bytes each. The interface between the two parts provides synchronization between the microprocessor accesses and the protocol logic working with the serial receive clock. Data Sheet 43 2000-09-14 PEB 20532 PEF 20532 Functional Overview Microprocessor/DMA Interface 32 byte Shadow part (not accessable by CPU) Receive Protocol Machine 32 byte Receive Pool (accessable by CPU) Figure 10 SCC Receive FIFO New receive data is announced to the CPU with an interrupt latest when the FIFO fill level reaches a chosen threshold level (selected with bitfield 'RFTH(1..0)' in register "CCR3H" on Page 167). Default value for this threshold level is 32 bytes in HDLC/PPP modes and 1 byte in ASYNC or BISYNC mode. If the SCC receive FIFO is completely filled, further incoming data is ignored and a receive data overflow condition ('RDO') is detected. As soon as the receive FIFO provides empty space, receive data is accepted again after a frame end or frame abort sequence. The automatically generated receive status byte (RSTA) will contain an 'RDO' indication in this case and the next incoming frame will be received in a normal way. Therefore no further CPU intervention is necessary to recover the SCC from an 'RDO' condition. A "frame" with 'RDO' status might be a mixture of a frame partly received before the 'RDO' event occured and the rest of this frame received after the receive FIFO again accepted data and the frame was still incoming. A quite arbitrary series of data or complete frames might get lost in case of an 'RDO' event. Every frame which is completely discarded because of an 'RDO' condition generates an 'RFO' interrupt. The SCC receive FIFO can be cleared by command 'RRES' in register CMDRH. Note that clearing the receive FIFO during operation might delete a frame end / block end indication. A frame which was already partly transferred cannot be "closed" in this case. A new frame received after receiver reset command will be appended to this "open" frame. Data Sheet 44 2000-09-14 PEB 20532 PEF 20532 Functional Overview 3.2.2.3 SCC FIFO Access Figure 11 and Figure 12 illustrate byte interpretation for Intel and Motorola 16-bit accesses to the transmit and receive FIFOs. XFIFO . Byte 32 . . . . . . . . Byte 5 . . Byte 4 . . Byte 3 . . Byte 2 . . Byte 1 . RFIFO . Byte 32 . . . . . . . . Byte 5 . . Byte 4 . . Byte 3 . . Byte 2 . . Byte 1 . D(15:8) D(7:0) D(15:8) D(7:0) Figure 11 XFIFO/RFIFO Word Access (Intel Mode) XFIFO . Byte 32 . . . . . . . . Byte 5 . . Byte 4 . . Byte 3 . . Byte 2 . . Byte 1 . RFIFO . Byte 32 . . . . . . . . Byte 5 . . Byte 4 . . Byte 3 . . Byte 2 . . Byte 1 . D(15:8) D(7:0) D(15:8) D(7:0) Figure 12 XFIFO/RFIFO Word Access (Motorola Mode) Data Sheet 45 2000-09-14 PEB 20532 PEF 20532 Functional Overview 3.2.3 Clocking System The SEROCCO-M includes an internal Oscillator (OSC) as well as two independent Baud Rate Generators (BRG) and two Digital Phase Locked Loop (DPLL) circuits. The transmit and receive clock can be generated either * externally, and supplied directly via the RxCLK and/or TxCLK pins (called external clock modes) * internally, by selecting - the internal oscillator (OSC) and/or the channel specific baud rate generator (BRG) - the internal DPLL, recovering the receive (and optionally transmit) clock from the receive data stream. (called internal clock modes) There are a total of 14 different clocking modes programmable via bit field 'CM' in register CCR0L, providing a wide variety of clock generation and clock pin functions, as shown in Table 8. The transmit clock pins (TxCLK) may also be configured as output clock and control signals in certain clock modes if enabled via bit 'TOE' in register CCR0L. The clocking source for the DPLL's is always the internal channel specific BRG; the scaling factor (divider) of the BRG can be programmed through BRRL and BRRH registers. There are two channel specific internal operational clocks in the SCC: One operational clock (= transmit clock) for the transmitter part and one operational clock (= receive clock) for the receiver part of the protocol logic. Note: The internal timers always run using the internal transmit clock. Table 7 Overview of Clock Modes Clock Type Receive Clock Source RxCLK Pins OSC, DPLL, BRG, TxCLK Pins, RxCLK Pins OSC, DPLL, BRG/BCR, BRG Generation Externally Internally 2, 3a, 6, 7a 3b, 7b Externally Internally 3a, 7a 2b, 6b 0b, 3b, 7b 0a, 2a, 4, 6a 1,5 Clock Mode 0, 1, 4, 5 Transmit Clock Data Sheet 46 2000-09-14 PEB 20532 PEF 20532 Functional Overview The internal structure of each SCC channel consists of a transmit protocol machine clocked with the transmit frequency fTRM and a receive protocol machine clocked with the receive frequency fREC. The clocks fTRM and fREC are internal clocks only and need not be identical to external clock inputs e.g. fTRM and TxCLK input pin. The features of the different clock modes are summarized in Table 8. Table 8 Channel Configuration Clock Modes of the SCCs Clock Sources Control Sources Clock Mode CCR0L: CM(2..0) 0a 0b 1 2a 2b 3a 3b 4 5a 5b 6a 6b 7a 7b CCR0L: to SSEL BRG 0 1 X 0 1 0 1 X 0 1 0 1 0 1 - OSC - RxCLK RxCLK RxCLK RxCLK - - - OSC OSC OSC OSC to DPLL - - - BRG BRG BRG - - - - BRG BRG BRG - to REC RxCLK RxCLK RxCLK DPLL DPLL DPLL BRG RxCLK RxCLK RxCLK DPLL DPLL DPLL BRG to TRM TxCLK BRG RxCLK TxCLK BRG/16 DPLL BRG TxCLK RxCLK TxCLK TxCLK BRG/16 DPLL BRG R- Strobe CD CD CD - CD CD CD CD - - - CD CD CD CD - - CD - - - - RCG (TSAR/ PCMRX) (TSAR/ PCMRX) - - - - Output via TxCLK Frame(if CCR0L: X- Strobe Sync Tx Rx TOE = `1') - - TxCLK - - - - TCG (TSAX/ PCMTX) (TSAX/ PCMTX) - - - - - - - - - - - - FSC - - - - - - - - FSC - BRG - - BRG/16 DPLL BRG TS-Control OST OSR - - - - - - - - - - BRG/16 DPLL BRG Note: If asynchronous operation is selected (asynchronous PPP, ASYNC mode), some clock mode frequencies can or must be divided by 16 as selected by the Bit Clock Rate bit CCR0L:BCR: Clock Mode 0a 0b 1 3b, 7b fREC fRxCLK/BCR fRxCLK/BCR fRxCLK/BCR fBRG/BCR fTRM fTxCLK fBRG fRxCLK/BCR fBRG/BCR When bit clock rate is `16' (bit BCR = '1'), oversampling (3 samples) in conjunction with majority decision is performed. BCR has no effect when using clock mode 2, 3a, 4, 5, 6, or 7a. Data Sheet 47 2000-09-14 PEB 20532 PEF 20532 Functional Overview Note: If one of the clock modes 0b, 6 or 7 is selected, the internal oscillator (OSC) should be enabled by clearing bit GMODE:OSCPD. This allows connection of an external crystal to pins XTAL1-XTAL2. The output signal of the OSC can be used for one serial channel, or for both serial channels (independent baud rate generators and DPLLs). Moreover, XTAL1 alone can be used as input for an externally generated clock. The first two columns of Table 8 list all possible clock modes configured via bit field 'CM' and bit 'SSEL' in register CCR0L. For example, clock mode 6b is choosen by writing a '6' to register CCR0L.CM(2:0) and by setting bit CCR0L.SSEL equal to '1'. The following 4 columns (grouped as 'Clock Sources') specify the source of the internal clocks. Columns REC and TRM correspond to the domain clock frequencies fREC and fTRM . The columns grouped as 'Control Sources' cover additional clock mode dependent control signals like strobe signals (clock mode 1), clock gating signals (clock mode 4) or synchronization signals (clock mode 5). The last column describes the function of signal TxCLK which in some clock modes can be enabled as output signal monitoring the effective transmit clock or providing a time slot control signal (clock mode 5). The following is an example of how to read Table 8: For clock mode 6b (row '6b') the TRM clock (column 'TRM') is supplied by the baudrate generator (BRG) output divided by 16 (source BRG/16). The BRG (column 'BRG') is derived from the internal oscillator which is supplied by pin XTAL1 and XTAL2. The REC clock (column 'REC') is supplied by the internal DPLL which itself is supplied by the baud rate generator (column 'DPLL') again. Note: The REC clock is DPLL clock divided by 16. If enabled by bit 'TOE' in register CCR0L the resulting transmit clock can be monitored via pin TxCLK (last column, row '6b'). Data Sheet 48 2000-09-14 PEB 20532 PEF 20532 Functional Overview The clocking concept is illustrated in a block diagram manner in the following figure: Additional control signals are not illustrated (please refer to the detailed clock mode descriptions below). TTL or CRYSTAL RxCLK XTAL1 XTAL2 Oscillator 0b 6a/b 7a/b 2a/b 3a/b BRG settings controlled by: register CCR0, bit field 'CM' selects the clock mode number register CCR0, bit 'SSEL' selects the additional a/b option DPLL 16:1 fDPLL f BRG/16 f RxCLK f TxCLK fBRG fBRG/16 fRxCLK f RxCLK 0a/b 1 5a/b 4 TxCLK RxD fTxCLK f DPLL f DPLL f BRG 3a 7a 0b 3b 7b 2b 6b 1 5a 0a 2a 6a 4 5b 2a/b 3b 7b 3a 6a/b 7a fTRM f BRG fREC Transmitter Receiver Figure 13 Clock Supply Overview Data Sheet 49 2000-09-14 PEB 20532 PEF 20532 Functional Overview Clock Modes 3.2.3.1 Clock Mode 0 (0a/0b) Separate, externally generated receive and transmit clocks are supplied to the SCC via their respective pins. The transmit clock may be directly supplied by pin TxCLK (clock mode 0a) or generated by the internal baud rate generator from the clock supplied at pin XTAL1 (clock mode 0b). In clock mode 0b the resulting transmit clock can be driven out to pin TxCLK if enabled via bit 'TOE' in register CCR0L. clock mode 0a XTAL1 XTAL2 clock supply RxCLK CTS, CxD, TCG CD, FSC, RCG TxCLK RTS Ctrl. 2 1 RxD Ctrl. TxD clock mode 0b or XTAL1 XTAL2 clock supply RxCLK CTS, CxD, TCG 1 OSC fBRG = fOSC /k K=(n+1)/2 M CD, FSC, RCG TxCLK RTS Ctrl. (tx clock monitor output) RxD Ctrl. TxD Figure 14 Clock Mode 0a/0b Configuration Data Sheet 50 2000-09-14 PEB 20532 PEF 20532 Functional Overview 3.2.3.2 Clock Mode 1 Externally generated RxCLK is supplied to both the receiver and transmitter. In addition, a receive strobe can be connected via CD and a transmit strobe via TxCLK pin. These strobe signals work on a per bit basis. This operating mode can be used in time division multiplex applications or for adjusting disparate transmit and receive data rates. Note: In Extended Transparent Mode, the above mentioned strobe signals provide byte synchronization (byte alignment). This means that the strobe signal needs to be detected once only to transmit or receive a complete byte. clock mode 1 XTAL1 XTAL2 clock supply RxCLK CTS, CxD, TCG CD, FSC, RCG TxCLK RTS Ctrl. 1 VSS (enables transmit) receive strobe transmit strobe RxD Ctrl. TxD RxD CD (rx strobe) RxCLK TxCLK (tx strobe) TxD Note: In extended transparent mode the strobe signals need to be detected once only to transmit or receive a complete byte. Thus byte alignment is provided in this mode. Figure 15 Clock Mode 1 Configuration Data Sheet 51 2000-09-14 PEB 20532 PEF 20532 Functional Overview 3.2.3.3 Clock Mode 2 (2a/2b) The BRG is driven by an external clock (RxCLK pin) and delivers a reference clock for the DPLL which is 16 times of the resulting DPLL output frequency which in turn supplies the internal receive clock. Depending on the programming of register CCR0L bit 'SSEL', the transmit clock will be either an external input clock signal provided at pin TxCLK in clock mode 2a or the clock delivered by the BRG divided by 16 in clock mode 2b. In the latter case, the transmit clock can be driven out to pin TxCLK if enabled via bit 'TOE' in register CCR0L. clock mode 2a XTAL1 XTAL2 clock supply BRG RxCLK CTS, CxD, TCG DPLL CD, FSC, RCG TxCLK RTS Ctrl. 2 1 RxD Ctrl. TxD clock mode 2b XTAL1 XTAL2 clock supply BRG RxCLK CTS, CxD, TCG DPLL 16:1 CD, FSC, RCG TxCLK RTS Ctrl. (tx clock monitor output) 1 RxD Ctrl. TxD Figure 16 Clock Mode 2a/2b Configuration Data Sheet 52 2000-09-14 PEB 20532 PEF 20532 Functional Overview 3.2.3.4 Clock Mode 3 (3a/3b) The BRG is fed with an externally generated clock via pin RxCLK. Depending on the value of bit 'SSEL' in register CCR0L the BRG delivers either a reference clock for the DPLL which is 16 times of the resulting DPLL output frequency (clock mode 3a) or delivers directly the receive and transmit clock (clock mode 3b). In the first case the DPLL output clock is used as receive and transmit clock. clock mode 3a XTAL1 XTAL2 clock supply BRG DPLL RxCLK CTS, CxD, TCG CD, FSC, RCG TxCLK RTS Ctrl. (tx clock monitor output) 1 RxD Ctrl. TxD clock mode 3b XTAL1 XTAL2 clock supply BRG RxCLK CTS, CxD, TCG CD, FSC, RCG TxCLK RTS Ctrl. (tx clock monitor output) 1 RxD Ctrl. TxD Figure 17 Clock Mode 3a/3b Configuration Data Sheet 53 2000-09-14 PEB 20532 PEF 20532 Functional Overview 3.2.3.5 Clock Mode 4 Separate, externally generated receive and transmit clocks are supplied via pins RxCLK and TxCLK. In addition separate receive and transmit clock gating signals are supplied via pins RCG and TCG. These gating signals work on a per bit basis. clock mode 4 XTAL1 XTAL2 clock supply RxCLK CTS, CxD, TCG CD, FSC, RCG TxCLK RTS Ctrl. 1 transmit clock gate signal receive clock gate signal 2 RxD Ctrl. TxD TxCLK 1 clock delay TCG TxD RxCLK RCG RxD Figure 18 Clock Mode 4 Configuration Data Sheet 54 2000-09-14 PEB 20532 PEF 20532 Functional Overview 3.2.3.6 Clock Mode 5a (Time Slot Mode) This operation mode has been designed for application in time-slot oriented PCM systems. Note: For correct operation NRZ data coding/encoding should be used. The receive and transmit clock are common for each channel and must be supplied externally via pin RxCLK. The SCC receives and transmits only during fixed time-slots. Either one time-slot - of programmable width (1 ... 512 bit, via TTSA and RTSA registers), and - of programmable location with respect to the frame synchronization signal (via pin FSC) or up to 32 time-slots - of constant width (8 bits), and - of programmable location with respect to the frame synchronization signal (via pin FSC) can be selected. The time-slot locations can be programmed independently for receive and transmit direction via TTSA/RTSA and PCMTX/PCMRX registers. Depending on the value programmed via those registers, the receive/transmit time-slot starts with a delay of 1 (minimum delay) up to 1024 clock periods following the frame synchronization signal. Figure 19 shows how to select a time-slot of programmable width and location and Figure 20 shows how to select one or more time-slots of 8-bit width. If bit 'TOE' in register CCR0L is set, the selected transmit time-slot(s) is(are) indicated at an output status signal via pin TxCLK, which is driven to `low' during the active transmit window. Bit 'TSCM' in register CCR1H determines whether the internal offset counters are continuously running even if no synchronization pulse is detected at FSC signal or stopping at their maximum value. In the continuous case the repetition rate of offset counter operation is 1024 transmit or receive clocks respectively. An FSC pulse detected earlier resets the counters and starts operation again. In the non-continuous case the time slot assigner offset counter is stopped after the counter reached its maximum value and is started again if an FSC pulse is detected. Data Sheet 55 2000-09-14 PEB 20532 PEF 20532 Functional Overview TTSA0..3: Transmit Time Slot Assignment Register 7 TTSA3 0 7 TTSA2 07 TTSA1 0 7 TTSA0 0 TCC 0 TTSN TCS TEPCM = '0': TPCM Mask Disabled FSC RxCLK active time slot TS delay (transmit): 1 + TTSN*8 + TCS (1...1024) TS delay (receive): 1 + RTSN*8 + RCS (1...1024) TS width (transmit): TCC (1...512 clocks) TS width (receive): RCC (1..512) RTSA0..3: Receive Time Slot Assignment Register 7 RTSA3 0 7 RTSA2 07 RTSA1 0 7 RTSA0 0 RCC 0 RTSN RCS REPCM = '0': RPCM Mask Disabled Figure 19 Selecting one time-slot of programmable delay and width Data Sheet 56 2000-09-14 PEB 20532 PEF 20532 Functional Overview Note: If time-slot 0 is to be selected, the DELAY has to be as long as the PCM frame itself to achieve synchronization (at least for the 2nd and subsequent PCM frames): DELAY = PCM frame length = 1 + xTSN*8 + xCS. xTSN and xCS have to be set appropriately. Example: Time-slot 0 in E1 (2.048 Mbit/s) system has to be selected. PCM frame length is 256 clocks. 256 = 1+ xTSN*8 + xCS. => xTSN = 31, xCS = 7. Note: In extended transparent mode the width xCC of the selected time-slot has to be n 8 bit because of character synchronization (byte alignment). In all other modes the width can be used to define windows down to a minimum length of one bit. Data Sheet 57 2000-09-14 PEB 20532 PEF 20532 Functional Overview TTSA0..3: Transmit Time Slot Assignment Register 7 TTSA3 0 7 TTSA2 0 7 TTSA1 0 7 TTSA0 0 TCC 1 TTSN TEPCM = '1': TPCM Mask Enabled TCS PCMTX0..3: Transmit PCM Mask Register 31 PCMTX3 24 23 PCMTX2 17 16 15 PCMTX1 87 PCMTX0 3 0 1 1 FSC RxCLK active time slot ... TS0 TS1 TS2 TS3 TS4 TS5 TS16 TS17 TS delay (transmit): 1 + TTSN*8 + TCS (1..1024) TS delay (receive): 1 + RTSN*8 + RCS (1..1024) 8 bit RTSA0..3: Receive Time Slot Assignment Register 7 RTSA3 0 7 RTSA2 0 7 RTSA1 0 7 RTSA0 0 RCC 1 RTSN RCS PCMRX0..3: Receive PCM Mask Register 31 PCMRX3 24 23 PCMRX2 16 15 REPCM = '1': TPCM Mask Enabled PCMRX1 87 PCMRX0 0 Figure 20 Selecting one or more time-slots of 8-bit width The common transmit and receive clock is supplied at pin RxCLK and the common frame synchronisation signal at pin FSC. The "strobe signals" for active time slots are generated internally by the time slot assigner block (TSA) independent in transmit and receive direction. When the transmit and receive PCM masks are enabled, bit fields 'TCC' and 'RCC' are ignored because of the constant 8-bit time slot width. Data Sheet 58 2000-09-14 PEB 20532 PEF 20532 Functional Overview clock mode 5a XTAL1 XTAL2 clock supply RxCLK CTS, CxD, TCG Time Slot Assigner (TSA) CD, FSC, RCG TxCLK RTS Ctrl. 1 time slot indicator signal RxD Ctrl. TxD n RxCLK 0 1 2 ... n 0 1 FSC TS delay TS width internal tx strobe TxCLK TS-Control TxD TS delay TS width internal rx strobe RxD Figure 21 Clock Mode 5a Configuration Note: The transmit time slot delay and width is programmable via bit fields 'TTSN', 'TCS' and 'TCC' in registers TTSA0..TTSA3. The receive time slot delay and width is programmable via bit fields 'RTSN', 'RCS' and 'RCC' in registers RTSA0..RTSA3. Data Sheet 59 2000-09-14 PEB 20532 PEF 20532 Functional Overview The following figures provide a more detailed description of the TSA internal counter operation and exceptional cases: clock mode 5a bit TSCM='0' (continuous mode) FSC RxCLK, TxCLK lo ad o ffs e t oc n t: o c n t := 1 02 4 - T S d e lay o cn t := 1 0 24 o c nt := 0 ... lo ad o ffs e t o cn t: o c nt := N , oc n t := 1 02 4 - T S d e lay N < T S de la y lo a d d u ra tion d c n t: M od e T E P C M /R E P C M = '0 ' d cn t := 0 d c n t := T S w id th - 1 ac tiv e tim e s lot M od e T E P C M /R E P C M = '1 ' d cn t := 0 dc n t := 2 5 5 ac tiv e tim e slo ts a c c ordin g P C M T X /P C M R X T S d ela y = 1 + xT S N *8 + x C S (1 ...1 0 2 4) E x c ep tio ns : a ) F S C p u ls e p erio d > 1 02 4 : T h e o ffse t c ou n te r oc n t w ill a uto m a ic ally re s tart afte r 1 02 4 clo c k c y c les a n d w ill b e res ta rte d a g ain b y th e la te F S C p u ls e! FSC T S d e la y + 10 2 4 c lo ck c yc le s o cn t s ta rt oc n t re sta rt oc n t re s tart b ) F S C p u ls e p erio d < (T S de la y + T S w id th ), i.e. F S C p u ls e de te cte d w hile du ratio n c o un te r s till a c tiv e : T h e o ffse t c ou n te r oc n t w ill a uto m a ic ally re s tart, b u t du ra tio n c o un te r d cn t c on tinu e s o p e ra tio n (tran s m it/re c e ive in a c tive tim e slo ts ) FSC < 10 2 4 c lo ck c yc le s o cn t s ta rt dc n t s ta rt o c nt re s tart Figure 22 Clock Mode 5a "Continuous Mode" Data Sheet 60 2000-09-14 PEB 20532 PEF 20532 Functional Overview Each frame sync pulse starts the internal offset counter with (1024 - TSdelay) whereas TSdelay is the configured value defining the start position. Whenever the offset counter reaches its maximum value 1024, it triggers the duration counter to start operation. If continuous mode is selected (bit CCR1H.TSCM='0') the offset counter continues starting with value 0 until another frame sync puls is detected or again the maximum value 1024 is reached. Once the duration counter is triggered it runs out independently from the offset counter, i.e. an active time slot period may overlap with the next frame beginning (frame sync event, refer to exception b) in Figure 22). clock mode 5a bit TSCM='1' (non continuous mode) A different behavior to clock mode 5a continous mode is given only in case of Exception a). Exceptions: a) FSC pulse period > 1024: The offset counter ocnt will stop on its maximum value 1024, which triggers the duration counter dcnt and will be restarted again by the 'late' FSC pulse! FSC TSdelay + 1024 clock cycles ocnt start ocnt stop ocnt start ocnt := TSdelay - 1 Figure 23 Clock Mode 5a "Non Continuous Mode" If non-continuous mode is selected (bit CCR1H.TSCM='1') the offset counter is stopped on its maximum value 1024 until another frame sync puls is detected. This allows frame sync periods greater than 1024 clock cycles, but the accesible part is limited by the range of TSdelay value (1..1024) plus TSwidth (1..512) or plus 256 clock cycles if the PCM mask is selected. Data Sheet 61 2000-09-14 PEB 20532 PEF 20532 Functional Overview 3.2.3.7 Clock Mode 5b (Octet Sync Mode) This operation mode has been designed for applications using Octet Synchronous PPP. It is based on clock mode 5a, but only 8-bit (octet) wide time slot operation is supported, i.e. bits TTSA1.TEPCM and RTSA1.REPCM must be set to '1'. Clock mode 5b provides octet alignment to time slots if Octet Synchronous PPP protocol mode or extended transparent mode is selected. Note: For correct operation NRZ data coding/encoding should be used. The receive and transmit clocks are separate and must be supplied at pins RxCLK and TxCLK. The SCC receives and transmits only during fixed octet wide time-slots of programmable location with respect to the octet synchronization signals (via pins OSR and OST) The time-slot locations can be programmed independently for receive and transmit direction via registers TTSA0..TTSA3 / RTSA0..RTSA3 and PCMTX0..PCMTX3 / PCMRX0..PCMRX3. Figure 24 shows how to select one or more octet wide time-slots. Bit 'TSCM' in register CCR1H determines whether the internal counters are continuously running even if no synchronization pulse is detected at OST/OSR signals or stopping at their maximum value. In the continuous case the repetition rate of operation is 1024 transmit or receive clocks respectively. An OST/OSR pulse detected earlier resets the corresponding offset counter and starts operation again. In the non-continuous case the transmit/receive time slot assigner offset counter is stopped after the counter reached its maximum value and is started again if an OST/ OSR pulse is detected. Data Sheet 62 2000-09-14 PEB 20532 PEF 20532 Functional Overview TTSA0..3: Transmit Time Slot Assignment Register 7 TTSA3 0 7 TTSA2 0 7 TTSA1 0 7 TTSA0 0 TCC 1 TTSN TCS TEPCM = '1': TPCM Mask Enabled PCMTX0..3: Transmit PCM Mask Register 31 PCMTX3 24 23 PCMTX2 17 16 15 PCMTX1 87 PCMTX0 3 0 1 1 OSR OST RxCLK TxCLK active time slot ... TS0 TS1 TS2 TS3 TS4 TS5 TS16 TS17 TS delay (transmit): 1 + TTSN*8 + TCS (1...1024) TS delay (receive): 1 + RTSN*8 + RCS (1...1024) 8 bit RTSA0..3: Receive Time Slot Assignment Register 7 RTSA3 0 7 RTSA2 0 7 RTSA1 0 7 RTSA0 0 RCC 1 RTSN RCS PCMRX0..3: Receive PCM Mask Register 31 PCMRX3 24 23 PCMRX2 16 15 REPCM = '1': TPCM Mask Enabled PCMRX1 87 PCMRX0 0 Figure 24 Selecting one or more octet wide time-slots The transmit and receive clocks are supplied at pins RxCLK and TxCLK. The Octet synchronisation signals are supplied at pins OSR and OST. The "strobe signals" for active time slots are generated internally by the time slot assigner blocks (TSA) independent in transmit and receive direction. Bit fields 'TCC' and 'RCC' are ignored because of the constant 8-bit time slot width. Data Sheet 63 2000-09-14 PEB 20532 PEF 20532 Functional Overview clock mode 5b XTAL1 XTAL2 clock supply RxCLK CTS, CxD, TCG, OST 1 Time Slot Assigner (RTSA) Time Slot Assigner (TTSA) CD, FSC, RCG, OSR TxCLK RTS 2 Ctrl. RxD Ctrl. TxD n RxCLK TxCLK OSR OST 0 1 2 ... n 0 TS delay TS width internal tx strobe TxD TS delay TS width internal rx strobe RxD Figure 25 Clock Mode 5b Configuration Note: The transmit time slot delay and width is programmable via bit fields 'TTSN', 'TCS' and 'TCC' in registers TTSA0..TTSA3. The receive time slot delay and width is programmable via bit fields 'RTSN', 'RCS' and 'RCC' in registers RTSA0..RTSA3. Data Sheet 64 2000-09-14 PEB 20532 PEF 20532 Functional Overview 3.2.3.8 Clock Mode 6 (6a/6b) This clock mode is identical to clock mode 2a/2b except that the clock source of the BRG is supplied at pin XTAL1. The BRG is driven by the internal oscillator and delivers a reference clock for the DPLL which is 16 times the resulting DPLL output frequency which in turn supplies the internal receive clock. Depending on the programming of register CCR0L bit 'SSEL', the transmit clock will be either an external input clock signal provided at pin TxCLK in clock mode 6a or the clock delivered by the BRG divided by 16 in clock mode 6b. In the latter case, the transmit clock can be driven out to pin TxCLK if enabled via bit 'TOE' in register CCR0L. clock mode 6a or XTAL1 OSC XTAL2 RxCLK CTS, CxD, TCG VSS clock supply 1 BRG DPLL CD, FSC, RCG TxCLK RTS Ctrl. RxD Ctrl. TxD clock mode 6b or XTAL1 OSC BRG XTAL2 RxCLK CTS, CxD, TCG CD, FSC, RCG VSS DPLL 16:1 TxCLK RTS (tx clock monitor output) Ctrl. RxD Ctrl. TxD Figure 26 Clock Mode 6a/6b Configuration Data Sheet 65 2000-09-14 PEB 20532 PEF 20532 Functional Overview 3.2.3.9 Clock Mode 7 (7a/7b) This clock mode is identical to clock mode 3a/3b except that the clock source of the BRG is supplied at pin XTAL1. The BRG is driven by the internal oscillator. Depending on the value of bit 'SSEL' in register CCR0L the BRG delivers either a reference clock for the DPLL which is 16 times the resulting DPLL output frequency (clock mode 7a) or delivers directly the receive and transmit clock (clock mode 7b). In clock mode 7a the DPLL output clocks receive and transmit data. clock mode 7a or XTAL1 OSC BRG XTAL2 RxCLK CTS, CxD, TCG CD, FSC, RCG VSS DPLL TxCLK RTS Ctrl. (tx clock monitor output) RxD Ctrl. TxD clock mode 7b or XTAL1 OSC XTAL2 RxCLK CTS, CxD, TCG VSS BRG CD, FSC, RCG TxCLK RTS Ctrl. (tx clock monitor output) RxD Ctrl. TxD Figure 27 Data Sheet Clock Mode 7a/7b Configuration 66 2000-09-14 PEB 20532 PEF 20532 Functional Overview 3.2.4 Baud Rate Generator (BRG) Each serial channel provides a baud rate generator (BRG) whose division factor is controlled by registers BRRL and BRRH. Whether the BRG is in the clocking path or not depends on the selected clock mode. Table 9 BRRL/BRRH Register and Bit-Fields Pos. 5..0 11..8 Name BRN BRM Default 0 0 Description Baud Rate Factor N range N = 0..63 Baud Rate Factor M, range M = 0..15 Register Bit-Fields Offset BRRL 38H/88H BRRH 39H/89H The clock division factor k is calculated by: k = ( N + 1 ) 2M f BRG = f in k 3.2.5 Clock Recovery (DPLL) The SCC offers the advantage of recovering the received clock from the received data by means of internal DPLL circuitry, thus eliminating the need to transfer additional clock information via a separate serial clock line. For this purpose, the DPLL is supplied with a `reference clock' from the BRG which is 16 times the expected data clock rate (clock mode 2, 3a, 6, 7a). The transmit clock may be obtained by dividing the output of the BRG by a constant factor of 16 (clock mode 2b, 6b; bit 'SSEL' in register CCR0L set) or also directly from the DPLL (clock mode 3a, 7a). The main task of the DPLL is to derive a receive clock and to adjust its phase to the incoming data stream in order to enable optimal bit sampling. The mechanism for clock recovery depends on the selected data encoding (see "Data Encoding" on Page 73). The following functions have been implemented to facilitate a fast and reliable synchronization: Data Sheet 67 2000-09-14 PEB 20532 PEF 20532 Functional Overview Interference Rejection and Spike Filtering Two or more edges in the same directional data stream within a time period of 16 reference clocks are considered to be interference and consequently no additional clock adjustment is performed. Phase Adjustment (PA) Referring to Figure 28, Figure 29 and Figure 30, in the case where an edge appears in the data stream within the PA fields of the time window, the phase will be adjusted by 1/ 16 of the data. Phase Shift (PS) (NRZ, NRZI only) Referring to Figure 28 in the case where an edge appears in the data stream within the PS field of the time window, a second sampling of the bit is forced and the phase is shifted by 180 degrees. Note: Edges in all other parts of the time window will be ignored. This operation facilitates a fast and reliable synchronization for most common applications. Above all, it implies a very fast synchronization because of the phase shift feature: one edge on the received data stream is enough for the DPLL to synchronize, thereby eliminating the need for synchronization patterns, sometimes called preambles. However, in case of extremely high jitter of the incoming data stream the reliability of the clock recovery cannot be guaranteed. The SCC offers the option to disable the Phase Shift function for NRZ and NRZI encodings by setting bit 'PSD' in register CCR0L to '1'. In this case, the PA fields are extended as shown in Figure 29. Now, the DPLL is more insensitive to high jitter amplitudes but needs more time to reach the optimal sampling position. To ensure correct data sampling, preambles should precede the data information. Figure 28, Figure 29 and Figure 30 explain the DPLL algorithms used for the different data encodings. Data Sheet 68 2000-09-14 PEB 20532 PEF 20532 Functional Overview Bit Cell DPLL Count 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Correction 0 +PA PS -PA 0 DPLL Output ITD01806 Figure 28 DPLL Algorithm (NRZ and NRZI Encoding, Phase Shift Enabled) Bit Cell DPLL Count 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Correction 0 +PA -PA 0 DPLL Output ITD04820 Figure 29 DPLL Algorithm (NRZ and NRZI Encoding, Phase Shift Disabled) Data Sheet 69 2000-09-14 PEB 20532 PEF 20532 Functional Overview Bit Cell (FM Coding) Bit Cell (Manchester Coding) DPLL Count Correction Transmit Clock Receive Clock ITD01807 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7 0 +PA - ignore -PA 0 +PA - ignore - Figure 30 DPLL Algorithm for FM0, FM1 and Manchester Encoding To supervise correct function when using bi-phase encoding, a status flag and a maskable interrupt inform about synchronous/asynchronous state of the DPLL. 3.2.6 SCC Timer Operation Each SCC provides a general purpose timer e.g. to support protocol functions. In all operating modes the timer is clocked by the effective transmit clock. In clock mode 5 (time-slot oriented mode) the clock source for the timer can be optionally switched to the frame sync clock (input pin FSC) by setting bit 'SRC' in register TIMR3. The timer is controlled by the CPU via access to registers CMDRL and TIMR0..TIMR3. The timer can be started any time by setting bit 'STI' in register CMDRL. After the timer has expired it generates a timer interrupt ('TIN'). With bit field 'CNT(2..0)' in register TIMR3 the number of automatic timer restarts can be programmed. If the maximum value '111' is entered, a timer interrupt is generated periodically, with the time period determined by bit field 'TVALUE' (registers TIMR0..TIMR3). The timer can be stopped any time by setting bit 'TRES' in register CMDRL to '1'. In HDLC Automode the timer is used internally for autonomous protocol functions (refer to the chapter "Automode" on Page 83). If this operating mode is selected, bit 'TMD' in register TIMR3 must be set to '1'. Data Sheet 70 2000-09-14 PEB 20532 PEF 20532 Functional Overview 3.2.7 SCC Serial Bus Configuration Mode Beside the point-to-point configuration, the SCC effectively supports point-to-multipoint (pt-mpt, or bus) configurations by means of internal idle and collision detection/collision resolution methods. In a pt-mpt configuration, comprising a central station (master) and several peripheral stations (slaves), or in a multimaster configuration, data transmission can be initiated by each station over a common transmit line (bus). In case more than one station attempts to transmit data simultaneously (collision), the bus has to be assigned to only one station. A collision-resolution procedure is implemented in the SCC. Bus assignment is based on a priority mechanism with rotating priorities. This allows each station a bus access within a predetermined maximum time delay (deterministic CSMA/CD), no matter how many transmitters are connected to the serial bus. Prerequisites for bus operation are: * NRZ encoding * `OR'ing of data from every transmitter on the bus (this can be realized as a wired-OR, using the TxD open drain capability) * Feedback of bus information (CxD input). The bus configuration is selected via bitfield SC(2:0) in register CCR0H. Note: Central clock supply for each station is not necessary if both the receive and transmit clock is recovered by the DPLL (clock modes 3a, 7a). This minimizes the phase shift between the individual transmit clocks. The bus configuration mode operates independently of the clock mode, e.g. also together with clock mode 1 (receive and transmit strobe operation). 3.2.8 Serial Bus Access Procedure The idle state of the bus is identified by eight or more consecutive `1's. When a device starts transmission of a frame, the bus is recognized to be busy by the other devices at the moment the first `zero' is transmitted (e.g. first `zero' of the opening flag in HDLC mode). After the frame has been transmitted, the bus becomes available again (idle). Note: If the bus is occupied by other transmitters and/or there is no transmit request in the SCC, logical `1' will be continuously transmitted on TxD. 3.2.9 Serial Bus Collisions and Recovery During the transmission, the data transmitted on TxD is compared with the data on CxD. In case of a mismatch (`1' sent and `0' detected, or vice versa) data transmission is immediately aborted, and idle (logical `1') is transmitted. Data Sheet 71 2000-09-14 PEB 20532 PEF 20532 Functional Overview HDLC/SDLC: Transmission will be initiated again by the SCC as soon as possible if the first part of the frame is still present in the SCC transmit FIFO. If not, an XMR interrupt is generated. Since a `zero' (`low') on the bus prevails over a `1' (high impedance) if a wired-OR connection is implemented, and since the address fields of the HDLC frames sent by different stations normally differ from one another, the fact that a collision has occurred will be detected prior to or at the latest within the address field. The frame of the transmitter with the highest temporary priority (determined by the address field) is not affected and is transmitted successfully. All other stations cease transmission immediately and return to bus monitoring state. Note: If a wired-OR connection has been realized by an external pull-up resistor without decoupling, the data output (TxD) can be used as an open drain output and connected directly to the CxD input. For correct identification as to which frame is aborted and thus has to be repeated after an XMR interrupt has occurred, the contents of SCC transmit FIFO have to be unique, i.e. SCC transmit FIFO should not contain data of more than one frame. For this purpose new data may be provided to the transmit FIFO only after 'ALLS' interrupt status is detected. 3.2.10 Serial Bus Access Priority Scheme To ensure that all competing stations are given a fair access to the transmission medium, a two-stage bus access priority scheme is supported by SEROCCO-M: Once a station has successfully completed the transmission of a frame, it is given a lower level of priority. This priority mechanism is based on the requirement that a station may attempt transmitting only when a determined number of consecutive `1's are detected on the bus. Normally, a transmission can start when eight consecutive `1's on the bus are detected (through pin CxD). When an HDLC frame has been successfully transmitted, the internal priority class is decreased. Thus, in order for the same station to be able to transmit another frame, ten consecutive `1's on the bus must be detected. This guarantees that the transmission requests of other stations are satisfied before the same station is allowed a second bus access. When ten consecutive `1's have been detected, transmission is allowed again and the priority class (of all stations) is increased (to eight `1's). Inside a priority class, the order of transmission (individual priority) is based on the HDLC address, as explained in the preceding paragraph. Thus, when a collision occurs, it is always the station transmitting the only `zero' (i.e. all other stations transmit a `one') in a bit position of the address field that wins, all other stations cease transmission immediately. Data Sheet 72 2000-09-14 PEB 20532 PEF 20532 Functional Overview 3.2.11 Serial Bus Configuration Timing Modes If a bus configuration has been selected, the SCC provides two timing modes, differing in the time interval between sending data and evaluation of the transmitted data for collision detection. * Timing mode 1 (CCR0H:SC(2:0) = `001') Data is output with the rising edge of the transmit clock via the TxD pin, and evaluated 1/2 a clock period later at the CxD pin with the falling clock edge. * Timing mode 2 (CCR0H:SC(2:0) = `011') Data is output with the falling clock edge and evaluated with the next falling clock edge. Thus one complete clock period is available between data output and collision detection. 3.2.12 Functions Of Signal RTS in HDLC Mode In clock modes 0 and 1, the RTS output can be programmed via register CCR1 (SOC bits) to be active when data (frame or character) is being transmitted. This signal is delayed by one clock period with respect to the data output TxD, and marks all data bits that could be transmitted without collision (see Figure 31). In this way a configuration may be implemented in which the bus access is resolved on a local basis (collision bus) and where the data are sent one clock period later on a separate transmission line. Collision TxD CxD RTS ITT00242 Figure 31 Request-to-Send in Bus Operation Note: For details on the functions of the RTS pin refer to "Modem Control Signals (RTS, CTS, CD)" on Page 76. 3.2.13 - - - - Data Encoding The SCC supports the following coding schemes for serial data: Non-Return-To-Zero (NRZ) Non-Return-To-Zero-Inverted (NRZI) FM0 (also known as Bi-Phase Space) FM1 (also known as Bi-Phase Mark) 73 2000-09-14 Data Sheet PEB 20532 PEF 20532 Functional Overview - Manchester (also known as Bi-Phase) The desired line coding scheme can be selected via bit field 'SC(2:0)' in register CCR0H. 3.2.13.1 NRZ and NRZI Encoding NRZ: The signal level corresponds to the value of the data bit. By programming bit 'DIV' (CCR1L register), the SCC may invert the transmission and reception of data. NRZI: A logical `0' is indicated by a transition and a logical `1' by no transition at the beginning of the bit cell. Transmit/ Receive Clock NRZ NRZI 0 Figure 32 1 1 0 0 1 0 ITD05313 NRZ and NRZI Data Encoding 3.2.13.2 FM0 and FM1 Encoding FM0: An edge occurs at the beginning of every bit cell. A logical `0' has an additional edge in the center of the bit cell, whereas a logical `1' has none. The transmit clock precedes the receive clock by 90. FM1: An edge occurs at the beginning of every bit cell. A logical `1' has an additional edge in the center of the bit cell, a logical `0' has none. The transmit clock precedes the receive clock by 90. Data Sheet 74 2000-09-14 PEB 20532 PEF 20532 Functional Overview Transmit Clock Receive Clock FM0 FM1 1 Figure 33 1 0 0 1 0 ITD01809 FM0 and FM1 Data Encoding 3.2.13.3 Manchester Encoding Manchester: In the first half of the bit cell, the physical signal level corresponds to the logical value of the data bit. At the center of the bit cell this level is inverted. The transmit clock precedes the receive clock by 90. The bit cell is shifted by 180 in comparison with FM coding. Transmit Clock Receive Clock Manchester 1 Figure 34 1 0 0 1 0 ITD01810 Manchester Data Encoding Data Sheet 75 2000-09-14 PEB 20532 PEF 20532 Functional Overview 3.2.14 Modem Control Signals (RTS, CTS, CD) 3.2.14.1 RTS/CTS Handshaking The SCC provides two pins (RTS, CTS) per serial channel supporting the standard request-to-send modem handshaking procedure for transmission control. A transmit request will be indicated by outputting logical `0' on the request-to-send output (RTS). It is also possible to control the RTS output by software. After having received the permission to transmit (CTS) the SCC starts data transmission. In the case where permission to transmit is withdrawn in the course of transmission, the frame is aborted and IDLE is sent. After transmission is enabled again by re-activation of CTS, and if the beginning of the frame is still available in the SCC, the frame will be re-transmitted (self-recovery). However, if the permission to transmit is withdrawn after the data available in the shadow part of the SCC transmit FIFO has been completely transmitted and the pool is released, the transmitter and the SCC transmit FIFO are reset, the RTS output is deactivated and an interrupt (XMR) is generated. Note: For correct identification as to which frame is aborted and thus has to be repeated after an XMR interrupt has occurred, the contents of SCC transmit FIFO have to be unique, i.e. SCC transmit FIFO should not contain data of more than one frame, which could happen if transmission of a new frame is started by providing new data to the transmitter too early. For this purpose the 'All Sent' interrupt (ISR1.ALLS) has to be waited for before providing new transmit data. Note: In the case where permission to transmit is not required, the CTS input can be connected directly to VSS and/or bit 'FCTS' (register CCR1H) may be set to '1'. Additionally, any transition on the CTS input pin, sampled with the transmit clock, will generate an interrupt indicated via register ISR1, if this function is enabled by setting the 'CSC' bit in register IMR1 to '0'. Data Sheet 76 2000-09-14 PEB 20532 PEF 20532 Functional Overview ~ ~ TxCLK ~ ~ TxD RTS ~ ~ CTS ~ ~ Sampling ITT00244 Figure 35 RTS/CTS Handshaking Beyond this standard RTS function, signifying a transmission request of a frame (Request To Send), in HDLC mode the RTS output may be programmed for a special function via SOC1, SOC0 bits in the CCR1L register. This is only available if the serial channel is operating in a bus configuration mode in clock mode 0 or 1. * If SOC1, SOC0 bits are set to `11', the RTS output is active (= low) during the reception of a frame. * If SOC1, SOC0 bits are set to `10', the RTS output function is disabled and the RTS pin remains always high. 3.2.14.2 Carrier Detect (CD) Receiver Control Similar to the RTS/CTS control for the transmitter, the SCC supports the carrier detect modem control function for the serial receiver if the Carrier Detect Auto Start (CAS) function is programmed by setting the 'CAS' bit in register CCR1H. This function is always available in clock modes 0, 2, 3, 6, 7 via the CD pin. In clock mode 1 the CD function is not supported. See Table 8 for an overview. If the CAS function is selected, the receiver is enabled and data reception is started when the CD input is detected to be high. If CD input is set to `low', reception of the current character (byte) is still completed. 3.2.15 Local Loop Test Mode To provide fast and efficient testing, the SCC can be operated in a test mode by setting the 'TLP' bit in register CCR2L. The on-chip serial data input and output signals (TxD, Data Sheet 77 2000-09-14 PEB 20532 PEF 20532 Functional Overview RxD) are connected, generating a local loopback. As a result, the user can perform a self-test of the SCC. TLP='0' SCC receive logic TLP='1' RxD SCC transmit logic IDLE '1' TLPO='0' TxD TLPO='1' Figure 36 SCC Test Loop Transmit data can be disconnected from pin TxD by setting bit TLPO in register CCR2L. Note: A sufficient clock mode must be used for test loop operation such that receiver and transmitter operate with the same frequencies depending on the clock supply (e.g. clock mode 2b or 6b). 3.3 Microprocessor Interface The communication between the CPU and SEROCCO-M is done via a set of directly accessible registers. The interface may be configured as Intel or Motorola type (refer to description of pin 'BM') with a selectable data bus width of 8 or 16 bit (refer to description of pin 'WIDTH'). The CPU transfers data to/from SEROCCO-M (via 64 byte deep FIFOs per direction and channel), sets the operating modes, controls function sequences, and gets status information by writing or reading control/status registers. All accesses can be done as byte or word accesses if enabled. If 16-bit bus width is selected, access to the lower/upper part of the data bus is determined by signals BHE/ BLE as shown in Table 10 (Intel mode) or by the upper and lower data strobe signals UDS/LDS as shown in Table 11 (Motorola mode). Table 10 BHE 0 0 BLE 0 1 Data Bus Access 16-bit Intel Mode Register Access Word access (16 bit) Byte access (8 bit), odd address Data Pins Used D(15:0) D(15:8) Data Sheet 78 2000-09-14 PEB 20532 PEF 20532 Functional Overview Table 10 BHE 1 1 BLE 0 1 Data Bus Access 16-bit Intel Mode Register Access Byte access (8 bit), even address no data transfer Data Pins Used D(7:0) - Table 11 UDS 0 0 1 1 LDS 0 1 0 1 Data Bus Access 16-bit Motorola Mode Register Access Word access (16 bit) Byte access (8 bit), even address Byte access (8 bit), odd address no data transfer Data Pins Used D(15:0) D(15:8) D(7:0) - Each of the two serial channels of SEROCCO-M is controlled via an identical, but completely independent register set (Channel A and B). Global functions that are common to or independent from the two serial channels are located in global registers. 3.4 External DMA Controller Support The SEROCCO-M comprises a 4-channel DMA interface for fast and effective data transfers using an external DMA controller. For both serial channels, a separate DMA Request output for Transmit (DRT) and Receive direction (DRR) as well as a DMA Acknowledgement input (DACK) is provided. The SEROCCO-M activates the DRR/DRT line as long as data transfers are needed from/to the specific FIFO (level triggered demand transfer mode of DMA controller). It is the responsibility of the DMA controller to perform the correct amount of bus cycles. Either read cycles will be performed if the DMA transfer has been requested from the receiver, or write cycles if DMA has been requested from the transmitter. If the DMA controller provides a DMA acknowledge signal (DACK pin, input to the SEROCCO-M), each bus cycle implicitly selects the top of the specific FIFO and neither address (via A0..A7) nor chip select need to be supplied (I/O to Memory transfers). If no DACK signal is provided, normal read/write operations (providing addresses) must be performed (Memory to Memory transfers). The SEROCCO-M deactivates the DRR/DRT line immediately after the last read/write cycle of the data transfer has started. Data Sheet 79 2000-09-14 PEB 20532 PEF 20532 Functional Overview 3.5 Interrupt Architecture For certain events in SEROCCO-M an interrupt can be generated, requesting the CPU to read status information from SEROCCO-M. The interrupt line INT/INT is asserted with the output characteristics programmed in bit field 'IPC(1..0)' in register "GMODE" on Page 122 (open drain/push pull, active low/high). Since only one interrupt request output is provided, the cause of an interrupt must be determined by the CPU by reading the interrupt status registers (GSTAR, ISR0, ISR1, ISR2, DISR, GPISL/GPISH). GSTAR GPI DMI ISA2 ISA1 ISA0 ISB2 ISB1 ISB0 GPIS GPIM DISR DIMR Channel B Channel A ISR2 (ch A) IMR2 (ch A) ISR1 (ch A) IMR1 (ch A) ISR0 (ch A) IMR0 (ch A) Figure 37 Interrupt Status Registers Each interrupt indication of registers ISR0, ISR1, ISR2, DISR and GPISL/GPISH can be selectively unmasked by resetting the corresponding bit in the corresponding mask registers IMR0, IMR1, IMR2, DIMR and GPIML/GPIMH. Use of these registers depends on the selected serial mode. If bit 'VIS' in register CCR0L is set to '1', masked interrupt status bits are visible in the interrupt status registers ISR0..ISR2. Interrupts masked in registers IMR0..IMR2 will not generate an interrupt though. A read access to the interrupt status registers clears the bits. A global interrupt mask bit (bit 'GIM' in register GMODE) suppresses interrupt generation at all. To enable the interrupt system after reset, this bit must be set to '0'. Data Sheet 80 2000-09-14 PEB 20532 PEF 20532 Functional Overview The Global Interrupt Status Register (GSTAR) serves as pointer to pending channel related interrupts and general purpose port interrupts. 3.6 3.6.1 General Purpose Port Pins GPP Functional Description General purpose port pins are provided on pins GP6, GP8, GP9 and GP10. If external DMA support is not enabled, pins GP0...GP2 are available as general purpose pins. Every pin is separately programmable via the General Purpose Port Direction registers GPDIRL/GPDIRH to operate as an output (bit GPnDIR='0') or as an input (bit GPnDIR='1', reset value). If defined as output, the state of the pin is directly controlled via the General Purpose Port Data registers GPDATL/GPDATH. Read access to these registers delivers the current state of all GPP pins (input and output signals). If defined as input, the state of the pin is monitored. The signal state of the corresponding GP pins is sampled with a rising edge of CLK and is readable via registers GPDATL/ GPDATH. 3.6.2 GPP Interrupt Indication The GPP block generates interrupts for transitions on each input signal. All changes may be indicated via interrupt (optional). To enable interrupt generation, the corresponding interrupt mask bit in registers GPIML/GPIMH must be reset to '0'. Bit GPI in the gloabl interrupt status register (GSTAR) is set to '1' if an interrupt was generated by any one or more of the the general purpose port pins. The GPP pin causing the interrupt can be located by reading the GPISL/GPISH registers. Data Sheet 81 2000-09-14 PEB 20532 PEF 20532 Detailed Protocol Description 4 Detailed Protocol Description The following Table 12 provides an overview of all supported protocol modes and . The desired protocol mode is selected via bit fields in the channel configuration registers CCR0L, CCR0H, CCR2L and CCR3L. Table 12 Protocol Mode Overview CCR3L ESS7 '0' Register CCR0H - Bit Field SM(1:0) = '00' Register CCR2L - Bit Field: (HDLC/SDLC/PPP protocol engine) HDLC Automode (LAP D / LAP B / SDLC-NRM) HDLC Address Mode 2 HDLC Address Mode 1 HDLC Address Mode 0 Signaling System #7 (SS7) Operation Bit Synchronous PPP Mode Octet Synchronous PPP Mode Asynchronous PPP Mode Extended Transparent Mode1) '11' '1' 16 bit 8 bit 16 bit 8 bit MDS '00' '00' '01' '01' '10' '10' '10' '10' ADM '1' '0' '1' '0' '1' '0' '0' '0' '00' '11' '01' '10' '00' PPPM '00' '1' '0' '0' Register CCR0H - Bit Field SM(1:0) = '11' Register CCR0L - Bit Field: (ASYNC protocol engine) Asynchronous Mode Isochronous Mode BCR '1' '0' Register CCR0H - Bit Field SM(1:0) = '10' Register CCR0L - Bit Field: (BISYNC protocol engine) Bisynchronous Mode Monosynchronous Mode 1) EBIM '1' '0' Extended transparent mode is a fully bit-transparent transmission/reception mode which is treated as submode of the HDLC/SDLC/PPP block. All modes are discussed in details in this chapter. Data Sheet 82 2000-09-14 PEB 20532 PEF 20532 Detailed Protocol Description 4.1 HDLC/SDLC Protocol Modes The HDLC controller of each serial channel (SCC) can be programmed to operate in various modes, which are different in the treatment of the HDLC frame in receive direction. Thus, the receive data flow and the address recognition features can be performed in a very flexible way satisfying almost any application specific requirements. There are 4 different HDLC operating modes which can be selected via register bits CCR2L:MDS[1:0] and CCR2L:ADM. 4.1.1 HDLC Submodes Overview The following table provides an overview of the different address comparison mechanisms in HDLC operating modes: Table 13 Mode Address Comparison Overview Address Field 16 bit Address Mode 2 Auto Mode 8 bit Address Mode 1 8 bit Recognized Address Bytes for a Match: High Address Byte FEH / FCH (1111 11 C/R 02) FEH / FCH (1111 11 C/R 02) RAH1 RAH1 RAH2 RAH2 RAL1 RAL2 FEH / FCH (1111 11 C/R 02) RAH1 RAH2 Address Mode 0 None don't care and and and and and and Low Address Byte RAL1 RAL2 RAL1 RAL2 RAL1 RAL2 don't care don't care don't care don't care don't care don't care 4.1.1.1 Automode Characteristics: Window size 1, random message length, address recognition. The SCC processes autonomously all numbered frames (S-, I-frames) of an HDLC protocol. The HDLC control field, I-field data of the frames and an additional status byte are temporarily stored in the SCC receive FIFO. Data Sheet 83 2000-09-14 PEB 20532 PEF 20532 Detailed Protocol Description Depending on the selected address mode, the SCC can perform a 2-byte or 1-byte address recognition. If a 2-byte address field is selected, the high address byte is compared with the fixed value FEH or FCH (group address) as well as with two individually programmable values in RAH1 and RAH2 registers. According to the ISDN LAPD protocol, bit 1 of the high byte address will be interpreted as COMMAND/RESPONSE bit (C/R), depending on the setting of the CRI bit in RAH1, and will be excluded from the address comparison. Similarly, two comparison values can be programmed in special registers (RAL1, RAL2) for the low address byte. A valid address will be recognized in case the high and low byte of the address field correspond to one of the compare values. Thus, the SCC can be called (addressed) with 6 different address combinations, however, only the logical connection identified through the address combination RAH1/RAL1 will be processed in the auto-mode, all others in the non auto-mode. HDLC frames with address fields that do not match any of the address combinations, are ignored by the SCC. In the case of a 1-byte address, only RAL1 and RAL2 will be used as comparison values. According to the X.25 LAPB protocol, the value in RAL1 will be interpreted as COMMAND and the value in RAL2 as RESPONSE. The address bytes can be masked to allow selective broadcast frame recognition. For further information see "Receive Address Handling" on Page 87. 4.1.1.2 Address Mode 2 Characteristics: address recognition, arbitrary window size. All frames with valid addresses (address recognition identical to auto-mode) are forwarded directly to the RFIFO. The HDLC control field, I-field data and an additional status byte are temporarily stored in the SCC receive FIFO. In address mode 2, all frames with a valid address are treated similarly. The address bytes can be masked to allow selective broadcast frame recognition. 4.1.1.3 Address Mode 1 Characteristics: address recognition high byte. Only the high byte of a 2-byte address field will be compared. The address byte is compared with the fixed value FEH or FCH (group address) as well as with two individually programmable values RAH1 and RAH2. The whole frame excluding the first address byte will be stored in the SCC receive FIFO. The address bytes can be masked to allow selective broadcast frame recognition. Data Sheet 84 2000-09-14 PEB 20532 PEF 20532 Detailed Protocol Description 4.1.1.4 Address Mode 0 Characteristics: no address recognition No address recognition is performed and each complete frame will be stored in the SCC receive FIFO. 4.1.2 HDLC Receive Data Processing The following figures give an overview about the management of the received frames in the different HDLC operating modes. The graphics show the actual HDLC frame and how SEROCCO-M interprets the incoming octets. Below that it is shown which octets are stored in the RFIFO and will thus be transferred into memory. 16 bit ADDR FLAG (high) (low) CTRL I-field (data) CRC16 /32 FLAG Automode 16 bit to RFIFO option 1) option 2) RSTA registers involved RAH1,2 RAL1,2 (address compare) RSTA Figure 38 HDLC Receive Data Processing in 16 bit Automode 8 bit ADDR FLAG (low) CTRL I-field (data) CRC16 /32 FLAG Automode 8 bit to RFIFO opt. 1) option 2) RSTA registers involved RAL1,2 (address compare) RSTA Figure 39 HDLC Receive Data Processing in 8 bit Automode Data Sheet 85 2000-09-14 PEB 20532 PEF 20532 Detailed Protocol Description 16 bit ADDR CRC16 data /32 FLAG Address Mode 2 16 bit FLAG (high) (low) to RFIFO option 1) option 2) RSTA registers involved RAH1,2 RAL1,2 (address compare) RSTA Figure 40 HDLC Receive Data Processing in Address Mode 2 (16 bit) 8 bit ADDR CRC16 data /32 FLAG Address Mode 2 8 bit FLAG (low) to RFIFO opt. 1) option 2) RSTA registers involved RAL1,2 (address compare) RSTA Figure 41 HDLC Receive Data Processing in Address Mode 2 (8 bit) 8 bit ADDR 16 bit ADDR CRC16 data /32 FLAG Address Mode 1 FLAG to RFIFO opt. 1) option 2) RSTA registers involved RAH1,2 (address compare) RSTA Figure 42 HDLC Receive Data Processing in Address Mode 1 Data Sheet 86 2000-09-14 PEB 20532 PEF 20532 Detailed Protocol Description CRC16 /32 FLAG Address Mode 0 FLAG data to RFIFO option 2) RSTA registers involved RSTA Figure 43 option 1) HDLC Receive Data Processing in Address Mode 0 The address field (8 bit address, 16 bit address or the high byte of a 16 bit address) can optionally be forwarded to the RFIFO (bit 'RADD' in register CCR3H) option 2) The 16 bit or 32 bit CRC field can optionally be forwarded to the RFIFO (bit 'RCRC' in register CCR3H) 4.1.3 Receive Address Handling The Receive Address Low/High Bytes (registers RAL1/RAH1 and RAL2/RAH2) can be masked on a per bit basis by setting the corresponding bits in the mask registers AMRAL1/AMRAH1 and AMRAL2/AMRAH2. This allows extended broadcast address recognition. Masked bit positions always match in comparison of the received frame address with the respective address fields in the Receive Address Low/High registers. This feature is applicable to all HDLC protocol modes with address recognition (auto mode, address mode 2 and address mode 1). It is disabled if all bits of mask bit fields AMRAL1/AMRAH1 and AMRAL2/AMRAH2 are set to `zero' (which is the reset value). Detection of the fixed group address FEH or FCH, if applicable to the selected operating mode, remains unchanged. As an option in the auto mode, address mode 2 and address mode 1, the 8/16 bit address field of received frames can be pushed to the receive data buffer (first one/two bytes of the frame). This function is especially useful in conjunction with the extended broadcast address recognition. It is enabled by setting control bit 'RADD' in register CCR3H. 4.1.4 HDLC Transmit Data Processing Two different types of frames can be transmitted: - I-frames and Data Sheet 87 2000-09-14 PEB 20532 PEF 20532 Detailed Protocol Description - transparent frames as shown below. Frames with automatic 8 or 16 bit Address and Control Byte Generation (Automode): 8 bit ADDR 16 bitADDR FLAG CTRL data CRC16 /32 FLAG XFIFO option 2) XAD1 XAD2 internally generated CRC16 FLAG data registers involved Frames without automatic Address and Control Byte Generation (Address Mode 2/1/0): /32 FLAG XFIFO option 2) option 2) Generation of the 16 or 32 bit CRC field can optionally be disabled by setting bit 'XCRC' in register CCR2H, in which case the CRC must be calculated and written into the last 2 or 4 bytes of the transmit FIFO, to immediately proceed closing flag. Figure 44 SCC Transmit Data Flow (HDLC Modes) For transmission of I-frames (selected via transmit command 'XIF' in register CMDRL), the address and control fields are generated autonomously by the SCC and the data in the corresponding transmit data buffer is entered into the information field of the frame. This is possible only if the SCC is operated in Automode. For (address-) transparent frames, the address and the control fields have to be entered in the transmit data buffer by software. This is possible in all operating modes and used also in auto-mode for sending U-frames. If bit 'XCRC' in register CCR2H is set, the CRC checksum will not be generated internally. The checksum has to be provided via the transmit data buffer as the last two Data Sheet 88 2000-09-14 PEB 20532 PEF 20532 Detailed Protocol Description or four bytes by software. The transmitted frame will be closed automatically only with a (closing) flag. Note: The SCC does not check whether the length of the frame, i.e. the number of bytes, to be transmitted makes sense according the HDLC protocol or not. 4.1.5 Shared Flags If the `Shared Flag' feature is enabled by setting bit 'SFLG' in register CCR1L the closing flag of a previously transmitted frame simultaneously becomes the opening flag of the following frame if there is one already available in the SCC transmit FIFO. In receive direction the SCC always expects and handles 'Shared Flags'. 'Shared Zeroes' of consecutive flags are also supported. 4.1.6 One Bit Insertion Similar to the zero bit insertion (bit stuffing) mechanism, as defined by the HDLC protocol, the SCC offers a feature of inserting/deleting a 'one' after seven consecutive `zeros' into the transmit/receive data stream, if the serial channel is operating in bus configuration mode. This method is useful if clock recovery is performed by DPLL. Since only NRZ data encoding is supported in a bus configuration, there are possibly long sequences without edges in the receive data stream in case of successive `0's received, and the DPLL may lose synchronization. Enabling the one bit insertion feature by setting bit 'OIN' in register CCR2H, it is guaranteed that at least after - 5 consecutive `1's a `0' will appear (bit stuffing), and after - 7 consecutive `0's a `1' will appear (one insertion) and thus a correct function of the DPLL is ensured. Note: As with the bit stuffing, the `one insertion' is fully transparent to the user, but it is not in accordance with the HDLC protocol, i.e. it can only be applied in proprietary systems using circuits that also implement this function, such as the PEB 20542 and and PEB 20525. 4.1.7 Preamble Transmission If enabled via bit 'EPT' in register CCR2H, a programmable 8-bit pattern is transmitted with a selectable number of repetitions after Interframe Timefill transmission is stopped and a new frame is ready to be sent out. The 8 bit preamble pattern can be programmed in register PREAMB and the repetition time in bit field 'PRE' of register CCR2H. Note: Zero Bit Insertion is disabled during preamble transmission. Data Sheet 89 2000-09-14 PEB 20532 PEF 20532 Detailed Protocol Description 4.1.8 CRC Generation and Checking In HDLC/SDLC mode, error protection is done by CRC generation and checking. In standard applications, CRC-CCITT algorithm is used. The Frame Check Sequence at the end of each frame consists of two bytes of CRC checksum. If required, the CRC-CCITT algorithm can be replaced by the CRC-32 algorithm, enabled via bit 'C32' in register CCR1L. In this case the Frame Check Sequence consists of four bytes. Optionally the internal handling of received and transmitted CRC checksum can be influenced via control bits 'RCRC', 'DRCRC' in register CCR3H and 'XCRC' in register CCR2H. Receive direction: If not disabled by setting bit 'DRCRC' (register CCR3H), the received CRC checksum is always assumed to be in the 2 (CRC-CCITT) or 4 (CRC-32) last bytes of a frame, immediately preceding a closing flag. If bit 'RCRC' is set, the received CRC checksum is treated as data and will be forwarded to the RFIFO, where it precedes the frame status byte. Nevertheless the received CRC checksum is additionally checked for correctness. If CRC checking is disabled with bit CCR3H:DRCRC, the limits for `Valid Frame' check are modified accordingly (refer to description of the Receive Status Byte, RSTA:VFR). Transmit direction: If bit 'XCRC' is set, the CRC checksum is not generated internally. The checksum has to be provided via the transmit data buffer by software. The transmitted frame will only be closed automatically with a (closing) flag. Note: The SCC does not check whether the length of the frame, i.e. the number of bytes, to be transmitted makes sense or not according the HDLC protocol. 4.1.9 Receive Length Check Feature The SCC offers the possibility to supervise the maximum length of received frames and to terminate data reception in the case that this length is exceeded. This feature is controlled via the special Receive Length Check Registers RLCRL/ RLCRH. The function is enabled by setting bit 'RCE' (Receive Length Check Enable) and the maximum frame length to be checked is programmed via bit field 'RL'. The maximum receive length can be determined as a multiple of 32-byte blocks as follows: MAX_LENGTH = (RL + 1) 32 , where RL is the value written to bit field 'RL'. Thus, the maximum length of receive frames can be programmed between 32 and 65536 bytes. All frames exceeding this length are treated as if they had been aborted by the remote station, i.e. the CPU is informed via Data Sheet 90 2000-09-14 PEB 20532 PEF 20532 Detailed Protocol Description - an 'RME' interrupt generated by the SCC, and - the receive abort indication 'RAB' in the Receive Status Byte (RSTA). Additionally an optional 'FLEX' interrupt is generated prior to 'RME', indicating that the maximum receive frame length was exceeded. Receive operation continues with the beginning of the next receive frame. 4.2 Point-to-Point Protocol (PPP) Modes PPP (as described in RFC1662) can work over 3 modes: asynchronous HDLC, synchronous HDLC, and octet synchronous. The SEROCCO-M supports asynchronous HDLC PPP over ISDN or DDS circuits as well as bit and octet synchronous HDLC PPP for use over dial-up connections. The octet synchronous mode of PPP protocol (RFC 1662) supports PPP over SONET applications. Both the asynchronous HDLC PPP mode, as well as the synchronous HDLC PPP modes are submodes of the HDLC mode. Either mode is selected by configuring SEROCCO-M for the standard HDLC mode. In addition the appropriate PPP mode is selected via bit field 'PPPM' in register CCR2L. The SEROCCO-M provides logic to convert an HDLC frame to an ASYNC character stream with the specified mapping functions. Layer 3 PPP functions are normally implemented in software. The PPP-support hardware allows software to perform segmentation and reassembly of PPP payloads, and allows SEROCCO-M to perform the asynchronous HDLC PPP or the synchronous HDLC PPP protocol conversions as required for the network interface. 4.2.1 Bit Synchronous PPP The SEROCCO-M transmits a data block, inserts HDLC Header (Opening Flag), and appends the HDLC Trailer (CRC, Ending Flag). Zero-bit stuffing algorithm is also performed. No character mapping is performed. The bit-synchronous PPP mode differs from the HDLC mode (address mode 0) only in the abort sequence: HDLC requires at least 7 consecutive '1' bits as abort sequence, whereas PPP requires at least 15 '1' bits. For receive operation SEROCCO-M monitors the incoming data stream for the Opening Flag (7E Hex) to identify the beginning of a HDLC packet. Subsequent bytes are part of data and are processed as normal HDLC packet including checking of CRC. 4.2.2 Octet Synchronous PPP The SEROCCO-M transmits a data block, inserts HDLC Header (Opening Flag), and appends the HDLC Trailer (CRC, Ending Flag). Beside this standard HDLC operation, zero-bit stuffing is not performed, but character mapping is performed. Data Sheet 91 2000-09-14 PEB 20532 PEF 20532 Detailed Protocol Description For receive operation SEROCCO-M monitors the incoming data stream for the Opening Flag (7E Hex) to identify the beginning of a HDLC packet. Subsequent bytes are part of data and are processed as normal HDLC packet including checking of CRC. Received mapped characters are unmapped. The abort sequence consists of the control escape character 7DH followed by a flag character 7EH (not stuffed). Between two frames, the interframe time fill character should be programmed to 7EH by setting bit CCR2H:ITF to '1'. Octet alignment is provided through the synchronization pulses in clock mode 5b. 4.2.3 Asynchronous PPP For transmit operation, SEROCCO-M inserts the HDLC header (Opening Flag), and appends the HDLC trailer (CRC, Ending Flag), surrounding the transmit data read from the XFIFO. Each octet (including HDLC framing flags and idle flags) is converted into async character format (1 start, 8 data bits, 1 stop bit) and then transmitted using the asynchronous character formatter block. Character mapping like in Octet Synchronous PPP mode is performed. In receive direction any async character is transferred into SEROCCO-M's ASYNC Character De-Formatting logic block, where it is translated back into the original information octet. Mapped characters are unmapped and the information octets are then transferred to the RFIFO (as in Octet Synchronous PPP mode). 4.2.4 Data Transparency in PPP Mode When transporting bit-files (as opposed to text files), or compressed files, the characters could easily represent MODEM control characters (such as CTRL-Q, CTRL-S) which the MODEM would not pass through. SEROCCO-M maintains an Async Control Character Map (ACCM) for characters 00-1F Hex. Whenever there is a mapped character in the data stream, the transmitter precedes that character with a control-escape character of 7DH. After the control-escape, the character itself is transmitted with bit 5 inverted. character e.g. 13H is mapped to 7DH, 33H). At the receive end, a 7DH character is discarded and the following character is modified by inverting bit 5 (e.g. if 7DH, 33H is received, the 7DH is discarded and the 33H is changed to 13H the original character). This character is received into RFIFO and included in CRC calculation, even if it is not mapped. The 32 lookup octet values (00H-1FH) are stored within the on-chip registers ACCM0..3. In addition to the ACCM, 4 user programmable characters (especially outside the range 00-1F Hex) can also be mapped using the control-escape sequence described above. These characters are specified in registers UDAC0..3. The receiver discards all characters which are received unmapped, but expected to be mapped because of ACCM0..3 and UDAC0..3 register contents. If this occurs within an Data Sheet 92 2000-09-14 PEB 20532 PEF 20532 Detailed Protocol Description HDLC frame, the unexpected characters are discarded before forwarded to the receive CRC checking unit. 7DH (control-escape) and 7EH (flag) octets in the data stream are mapped in general. The sequence of mapping control logic is: 1. 7DH and 7EH octets, 2. ACCM0..3, 3. UDAC0..3. This mechanism is applied to asynchronous HDLC PPP mode as well as to octet synchronous HDLC PPP mode. Data Sheet 93 2000-09-14 PEB 20532 PEF 20532 Detailed Protocol Description ACCM0..3: Async Control Character Map Register ACCM3 7 1F 1E 0 0 ... ... 0 7 ACCM2 3 15 14 13 12 11 0 0 1 0 0 0 7 ... ... ACCM1 0 7 ACCM0 0 00 0 UDAC0..3: User Defined Async Control Character Map Register 7 UDAC3 0 7 UDAC2 0 7 UDAC1 0 7 UDAC0 0 7Eh 7Eh 7Eh 20h data in transmit FIFO: 13H 20H 01H 02H HDLC framing: PPP mapping: 7EH 13H 20H 01H 02H 7EH 7EH 7DH 33H 7DH 00H 01H 02H 7EH serial line received character: PPP unmapping : data in receive FIFO: 7EH 7DH 33H 7DH 00H 01H 02H 7EH 7EH 13H 20H 01H 02H 7EH 13H 20H 01H 02H Note: CRC generation/checking is assumed to be disabled in this example; according the PPP mapping/ unmapping, CRC characters are treated as 'data' characters being mapped/unmapped if necessary . Figure 45 PPP Mapping/Unmapping Example Data Sheet 94 2000-09-14 PEB 20532 PEF 20532 Detailed Protocol Description 4.3 Extended Transparent Mode Characteristics: fully transparent When programmed in the extended transparent mode via the CCR2L register (bits MDS1, MDS0, ADM = `111'), the SCC performs fully transparent data transmission and reception without HDLC framing, i.e. without * FLAG insertion and deletion * CRC generation and checking * bit stuffing. This feature can be profitably used e.g. for: * user specific protocol variations * line state monitoring, or * test purposes, in particular for monitoring or intentionally generating HDLC protocol rule violations (e.g. wrong CRC) Character or octet boundary synchronization can be achieved by using clock mode 5 or clock mode 1 with an external receive strobe input to pin CD. Note: Data is transmitted and received with the least significant bit (LSB) first. 4.4 4.4.1 Asynchronous (ASYNC) Protocol Mode Character Framing Character framing is achieved by start and stop bits. Each data character is preceded by one Start bit and terminated by one or two stop bits. The character length is selectable from 5 up to 8 bits. Optionally, a parity bit can be added which complements the number of ones to an even or odd quantity (even/odd parity). The parity bit can also be programmed to have a fixed value (Mark or Space). The character format configuration is performed via appropriate bit fields in registers CCR3L/CCR3H. Figure 46 shows the asynchronous character format. Data Sheet 95 2000-09-14 PEB 20532 PEF 20532 Detailed Protocol Description Character Frame D0 (LSB) D5 D1 D2 D3 D4 Par. D6 Par. D7 Parity Par. 1 Start Bit 5 to 8 Data Bits (6 to 9 Bits with Parity) 1 or 2 Stop Bits ITD01804 Figure 46 Asynchronous Character Frame 4.4.2 Data Reception The SCC offers the flexibility to combine clock modes, data encoding and data sampling in many different ways. However, only definite combinations make sense and are recommended for correct operation: 4.4.2.1 Asynchronous Mode Prerequisites: * Bit clock rate 16 selected (register CCR0L, bit BCR = `1') * Clock mode 0, 1, 3b, 4, or 7b selected (register CCR0L, bit field 'CM') * NRZ data encoding selected (register CCR0H, bit field 'SC') The receiver which operates with a clock rate equal to 16 times the nominal (expected) data bit rate, synchronizes itself to each character by detecting and verifying the start bit. Since character length, parity and stop bit length is known, the ensuing valid bits are sampled. Oversampling (3 samples) around the nominal bit center in conjunction with majority decision is provided for every received bit (including start bit). The synchronization lasts for one character, the next incoming character causes a new synchronization to be performed. As a result, the demand for high clock accuracy is reduced. Two communication stations using the asynchronous procedure are clocked independently, their clocks need not be in phase or locked to exactly the same frequency but, in fact, may differ from one another within a certain range. 4.4.2.2 Isochronous Mode Prerequisites: * Bit clock rate 1 selected (register CCR0L bit BCR = `0') Data Sheet 96 2000-09-14 PEB 20532 PEF 20532 Detailed Protocol Description * Clock mode 2, 3a, 6, or 7a (DPLL mode) has to be used in conjunction with FM0, FM1 or Manchester encoding (register CCR0L/CCR0H bit fields 'CM' and 'SC'). The isochronous mode uses the asynchronous character format. However, each data bit is only sampled once (no oversampling). In clock modes 0 ,1 and 4, the input clock has to be externally phase locked to the data stream. This mode allows much higher transfer rates. Clock modes 3b and 7b are not recommended due to difficulties with bit synchronization when using the internal baud rate generator. In clock modes 2, 3a, 6, and 7a, clock recovery is provided by the internal DPLL. Correct synchronization of the DPLL is achieved if there are enough edges within the data stream, which is generally ensured only if Bi-Phase encoding (FM0, FM1 or Manchester) is used. 4.4.2.3 Storage of Receive Data If the receiver is enabled, received data is stored in the SCC receive FIFO (the LSB is received first). Moreover, the CD input may be used to control data reception. Character length, number of stop bits and the optional parity bit are checked. Storage of parity bits can be disabled. Errors are indicated via interrupts. Additionally, the character specific error status (framing and parity) can optionally be stored in the SCC receive FIFO. Filling of the the SCC receive FIFO is controlled by * * * * a programmable threshold level (bit field 'RFTH' in register CCR3H), the selected data format (bit 'RFDF' in register CCR3H), the parity storage selection (bit 'DPS' in register CCR3H), detection of the programmable Termination Character (bit 'TCDE' in register CCR3L and bit field 'TC' in register TCR). Additionally, the time-out event interrupt as an optional status information indicates that a certain time (refer to register TOLEN) has elapsed since the reception of the last character. 4.4.3 Data Transmission The selection of asynchronous or isochronous operation has no further influence on the transmitter. The bit clock rate is solely a dividing factor for the selected clock source. Transmission of the contents of the SCC transmit FIFO starts after the 'XF' command is issued (the LSB is sent out first). Further data is requested by an 'XPR' interrupt (or by DMA). The character frame for each character, consisting of start bit, the character itself with defined character length, optionally generated parity bit and stop bit(s) is assembled. After finishing transmission (indicated by the `ALLS' interrupt), IDLE sequence (logical `1') is transmitted on pin TxD. Data Sheet 97 2000-09-14 PEB 20532 PEF 20532 Detailed Protocol Description Additionally, the CTS signal may be used to control data transmission. 4.4.4 4.4.4.1 Special Functions Break Detection/Generation Break generation: On issuing the transmit break command (bit 'XBRK' in register CCR3L), the TxD pin is immediately forced to physical `0' level with the next following transmit clock edge, and released with the first transmit clock edge after this command is reset again by software. Break detection: The SCC recognizes the break condition upon receiving consecutive (physical) `0's for the defined character length, the optional parity and the selected number of stop bits (`zero' character and framing error). The `zero' character is not pushed to RFIFO. If enabled, the 'Break' interrupt (BRK) is generated. The break condition will be present until a `1' is received which is indicated by the `Break Terminated' interrupt (BRKT). 4.4.4.2 In-band Flow Control by XON/XOFF Characters Programmable XON and XOFF characters: The XON/XOFF registers contain the programmable values for XON and XOFF characters. The number of significant bits in a register is determined by the programmed character length via bit field 'CHL' in register CCR3L. Additionally, two programmable eight-bit values in registers MXON and MXOFF serve as masks for the characters XON and XOFF, respectively: A `1' in any mask bit position has the effect that no comparison is performed between the corresponding bits in the received characters (`don't cares') and the XON/XOFF value. At RESET, the masks are zero'ed, i.e. all bit positions will be compared. A received character is considered to be recognized as a valid XON or XOFF character - if it is correctly framed (correct length), - if its bits match the ones in the XON or XOFF registers over the programmed character length, - if it has correct parity (if applicable). Received XON and XOFF characters are stored in the SCC receive FIFO, as any other characters, when bit 'DXS' is set to '0' in register CCR3L. Otherwise they are not stored in the receive FIFO. Data Sheet 98 2000-09-14 PEB 20532 PEF 20532 Detailed Protocol Description In-Band Flow Control of Transmitted Characters: Recognition of an XON or XOFF character causes always a corresponding maskable interrupt status to be generated. Further action depends on the setting of control bit 'FLON' (Flow Control On) in register CCR2H: 0: No further action is automatically taken by the SCC. 1: The reception of an XOFF character automatically turns off the transmitter after the currently transmitted character (if any) has been shifted out completely (entering XOFF state). The reception of an XON character automatically makes the transmitter resume transmitting (entering XON state). After hardware RESET, bit CCR2H:FLON is `0'. When bit CCR2H:FLON is programmed from `0' to `1', the transmitter is first in the `XON state', until an XOFF character is received. When bit CCR2H:FLON is programmed from `1' to `0', the transmitter always goes in the `XON state', and transmission is only controlled by the user and by the CTS signal input. The in-band flow control of the transmitter via received XON and XOFF characters can be combined with control via CTS pin, i.e. the effect of the CTS pin is independent of whether in-band control is used or not. The transmitter is enabled only if CTS is `low' and XON state has been reached. Transmitter Status Bit: The status bit `Flow Control Status' (bit 'FCS' in register STARL) indicates the current state of the transmitter, as follows: 0: if the transmitter is in XON state, 1: if the transmitter is in XOFF state. Note: The transmitter cannot be turned off by software without disrupting data possibly remaining in the transmit FIFO. Flow Control for Received Data: After writing a character value to register TICR (Transmit Immediate Character, 'TIC') its character contents is inserted into the outgoing character stream * immediately upon writing this register by the microprocessor if the transmitter is in IDLE state. If no further characters (transmit FIFO empty) are to be transmitted, i.e. the transmitter returns to IDLE state after transmission of the 'TIC' and an ALLS (All Sent) interrupt will be generated. * after the end of a character currently being transmitted if the transmitter is not in IDLE state. This does not affect the contents of the transmit FIFO. Transmission of characters from transmit FIFO is resumed after the 'TIC' is send out. Data Sheet 99 2000-09-14 PEB 20532 PEF 20532 Detailed Protocol Description Transmission via this register is possible even when the transmitter is in XOFF state (however, CTS must be `low'). The 'TIC' value is an eight-bit value. The number of significant bits is determined by the programmed asynch character length via bit field 'CHL' in register CCR3L. Parity value (if programmed) and selected number of stop bits are automatically appended, equal to the characters provided via the transmit data buffer. The usage of 'TIC' is independent of in-band flow control mechanism, i.e. is not affected by bit 'FLON' in register CCR2H anyway. To control multiple accesses to register TICR, an additional status bit STARL:TEC (TIC Executing) is provided which signals that the transmission command of currently programmed 'TIC' is accepted but not yet completely executed. Further access to register TICR is only allowed if bit STARL:TEC is `0' again. 4.4.4.3 Out-of-band Flow Control Transmitter: The transmitter output is enabled if CTS signal is `LOW' AND the XON state is reached in case of in-band flow control is enabled. If the in-band flow control is disabled (CCR2H:FLON = `0'), the transmitter is only controlled by the CTS signal. Nevertheless setting bit CCR1H:FCTS = `1' allows the transmitter to send data independent of the condition of the CTS signal, the in-band flow control (XON/XOFF) mechanism would still be operational if enabled via bit CCR2H:FLON = `1'. Receiver: For some applications it is desirable to provide means of out-of-band flow control to indicate to the far end transmitter that the local receiver's buffer is getting full. This flow control can be used between two DTEs as shown in Figure 47 and between a DTE and a DCE (MODEM) as shown in Figure 48 that supports this kind of bi-directional flow control. Setting bit CCR1H:FRTS = `1' and CCR1H:RTS = `0' invokes this out-of-band flow control for the receiver. When the shadow part of the receive FIFO has reached a set threshold of 28 bytes, the RTS signal is forced inactive (high). When the shadow part of the receive FIFO is empty, the RTS is re-asserted (low). Note that the data is immediately transferred from the shadow receive FIFO to the user accessible RFIFO (as long as there is space available). So when the shadow receive FIFO reaches the 28 bytes threshold, there is 4 more byte storage available before overflow can occur. This allows sufficient time for the far end transmitter to react to the change in the RTS signal and stop sending more data. Figure 47 shows the connection between two SCC devices as DTEs. The RTS of DTEA (SCC) feeds the CTS input of the second DTE-B (another SCC). For example while Data Sheet 100 2000-09-14 PEB 20532 PEF 20532 Detailed Protocol Description DTE-A is receiving data and its receive FIFO threshold is reached, the RTS signal goes in-active 'HIGH' forcing the CTS of DTE-B to become in-active indicating that transmission has to stop after finishing the current character. Both DTE devices should also be using the CTS signal to flow control their transmitters. When the shadow receive FIFO in DTE-A is cleared its RTS goes active (low) and this signals the far end DTE-B to resume transmission. Data flow control from DTE-B to DTE-A works in the same way. DTE A RS232c Signals SEROCCO-M TxD RxD (drivers not shown) DTE B SEROCCO-M TxD RxD RTS CTS RTS CTS ITS08517 Figure 47 Out-of-Band DTE-DTE Bi-directional Flow Control Data Sheet 101 2000-09-14 PEB 20532 PEF 20532 Detailed Protocol Description Figure 48 shows an SCC as a DTE connected to a DCE (MODEM equipment). The RTSA feeds the RTSB input of the DCE (MODEM equipment) that supports bidirectional flow control. So when the DTE-A's receiver threshold is reached, the RTSA signal goes inactive 'HIGH' which is sensed by the DCE and it stops transmitting. Similarly if the DCE's receiver threshold is reached, it deactivates the CTSB ('HIGH') and causes the DTE to stop transmission. These types of DCEs have fairly deep buffers to ensure that it can continue to receive data from the line even though it is unable to pass the data to the DTE for short periods of time. Note that a SCC can also be used in the DCE equipment as shown. Exchange of signals (e.g. RTS to CTS) is necessarily inside the DCE equipment. DTE A RS232c Signals SEROCCO-M TxD RxD (drivers not shown) TxD RxD DCE B MODEM 1) SEROCCO-M TxD RxD RTS CTS RTS CTS RTS CTS 1) Some MODEMs support bi-directional flow control. Figure 48 Out-of-Band DTE-DCE Bi-directional Flow Control RTS and CTS are used to indicate when the local receiver's buffer is nearly full. This alerts the far end transmitter to stop transmission. The combination of transmitter and receiver out-of-band control features mentioned above enables data to be exchanged between two devices without software intervention for flow control. 4.5 4.5.1 BISYNC Protocol Mode Character Framing Character oriented protocols achieve synchronization between transmitting and receiving station by means of special SYN characters. Two examples are the MONOSYNC and IBM's BISYNC procedures. BISYNC has two starting SYN characters Data Sheet 102 2000-09-14 PEB 20532 PEF 20532 Detailed Protocol Description while MONOSYNC uses only one SYN. Figure 49 gives an example of the message format. SYN (SYNL) SYN (SYNH) SOH Header STX Text (Data) ETX CRC 2 Leading SYN Characters Start of Header Start of Text End of Text Frame Checking Sequence ITD01805 Figure 49 BISYNC Message Format The SYN character, its length, the length of data characters and additional parity generation are programmable: * 1 SYN character with 6 or 8 bit length (MONOSYNC), programmable via register SYNCL. * 2 SYN characters with 6 or 8 bit length each (BISYNC), programmable via registers SYNCH/SYNCL. * Data character length may vary from 5 to 8 bits (bit field 'CHL' in register CCR3L). * Parity information (even/odd parity, mark, space) may be appended to the character (bit 'PARE' and bit field 'PAR' in register CCR3H). 4.5.2 Data Reception The receiver is generally activated by setting bit 'RAC' in register CCR3L. Additionally, the CD signal may be used to control data reception depending on the selected clock mode. After issuing the HUNT command, the receiver monitors the incoming data stream for the presence of specified SYN character(s). However, data reception is still disabled. If synchronization is gained by detecting the SYN character(s), an SCD interrupt is generated and all following data is pushed to the receive FIFO, i.e. control sequences, data characters and optional CRC frame checking sequence (the LSB is received first). In normal operation, SYN characters are excluded from storage to receive FIFO. SYN character length can be specified independently of the selected data character length. If required, the character parity bit and/or parity status is stored together with each data byte in the receive FIFO. As an option, the loading of SYN characters in receive FIFO may be enabled by setting the bit 'SLOAD' in register CCR3L. Note that in this case SYN characters are treated as data. Consequently, for correct operation it must be guaranteed that SYN character Data Sheet 103 2000-09-14 PEB 20532 PEF 20532 Detailed Protocol Description length equals the character length + optional parity bit. This is the user's responsibility by appropriate software settings. Filling of the receive FIFO is controlled by a programmable threshold level. Reception is stopped if 1. the receiver is deactivated by resetting the bit CCR3L:RAC bit, or 2. the CD signal goes inactive (if Carrier Detect Auto Start is enabled in register CCR1H), or 3. the CMDRH:HUNT command is issued again, or 4. the Receiver Reset command (CMDRH:RRES) is issued, or 5. a programmed Termination Character has been found (optional). On actions 1. and 2., reception remains disabled until the receiver is activated again. After this is done, and generally in cases 3. and 4., the receiver returns to the (nonsynchronized) Hunt state. In case 5. a HUNT command has to be issued. Reception of data is internally disabled until synchronization is regained. Note: Further checking of frame length, extraction of text or data information and verifying the Frame Checking Sequence (e.g. CRC) has to be done by the microprocessor. 4.5.3 Data Transmission Transmission of data provided in the memory is started after the Transmit Frame ('XF') command is issued (the LSB is sent out first). Additionally, the CTS signal may be used to control data transmission. The message frame is assembled by appending all data characters to the specified SYN character(s) until Transmit Message End condition is detected ('XME' command in interrupt mode or, in DMA mode, when the number of characters specified in XBCL/XBCH have been transferred). Internally generated parity information may be added to each character (SYN, CRC and Preamble characters are excluded). If enabled via CRC Append bit (bit 'CAPP' in register CCR2H), the internally calculated CRC checksum (16 bit) is added to the message frame. Selection between CRC-16 and CRC-CCITT algorithms is provided. Note: - Internally generated SYN characters are always excluded from CRC calculation, - CRC checksum (2 bytes) is sent without parity. The internal CRC generator is automatically initialized before transmission of a new frame starts. The initialization value is selectable. After finishing data transmission, interframe-time-fill (SYN characters or IDLE) is automatically sent. A transmit data underrun condition in the XFIFO is indicated with an 'XDU' interrupt. Nevertheless, transmission continues inserting SYN characters into the data stream until Data Sheet 104 2000-09-14 PEB 20532 PEF 20532 Detailed Protocol Description new data is available in the transmit FIFO. Inserted SYN characters are not part of the frame and thus not used for CRC calculation. 4.5.4 4.5.4.1 Special Functions Preamble Transmission If enabled via register CCR2H, a programmable 8-bit pattern (register PREAMB) is transmitted with a selectable number of repetitions after interframe-time-fill transmission is stopped and a new frame is ready to be sent out. Note: If the preamble pattern equals the SYN pattern, reception is triggered by the preamble. 4.6 Procedural Support (Layer-2 Functions) When operating in the auto mode, the SCC offers a high degree of protocol support. In addition to address recognition, the SCC autonomously processes all (numbered) S- and I-frames (window size 1 only) with either normal or extended control field format (modulo-8 or modulo-128 sequence numbers - selectable via register CCR2H bit 'MCS'). The following functions will be performed: - - - - - - - - - updating of transmit and receive counter evaluation of transmit and receive counter processing of S commands flow control with RR/RNR generation of responses recognition of protocol errors transmission of S commands, if acknowledgement is not received continuous status query of remote station after RNR has been received programmable timer/repeater functions. In addition, all unnumbered frames are forwarded directly to the processor. The logical link can be initialized by software at any time (Reset HDLC Receiver by RRES command in register CMDRH). Additional logical connections can be operated in parallel by software. 4.6.1 Full-Duplex LAPB/LAPD Operation Initially (i.e. after RESET), the LAP controllers of the two serial channels are configured to function as a combined (primary/secondary) station, where they autonomously perform a subset of the balanced X.25 LAPB/ISDN LAPD protocol. Data Sheet 105 2000-09-14 PEB 20532 PEF 20532 Detailed Protocol Description Reception of Frames: The logical processing of received S-frames is performed by the SCC without interrupting the host. The host is merely informed by interrupt of status changes in the remote station (receiver ready / receiver not ready) and protocol errors (unacceptable N(R), or S-frame with I-field). I-frames are also processed autonomously and checked for protocol errors. The I-frame will not be accepted in the case of sequence errors (no interrupt is forwarded to the host), but is immediately confirmed by an S-response. If the host sets the SCC into a `receive not ready' status, an I-frame will not be accepted (no interrupt) and an RNR response is transmitted. U-frames are always stored in the RFIFO and forwarded directly to the host. The logical sequence and the reception of a frame in auto mode is illustrated in Figure 50. Note: The state variables N(S), N(R) are evaluated within the window size 1, i.e. the SCC checks only the least significant bit of the receive and transmit counter regardless of the selected modulo count. Data Sheet 106 2000-09-14 PEB 20532 PEF 20532 Detailed Protocol Description 1 Rec.Activ RR,REJSREJ , Y Y RNR I Frame U Frame CRC Error or Abort ? N Prot. Error ? N CRC Error or Abort ? N Prot. Error ? N Y Set RAB Y Aborted ? N CRC Error ? N N Aborted ? Y Set RAB Y Y Int : PCE RESET RRNR 1 Int : PCE Set RRNR 1 1 Int :RME Set CRCE Y Prot. Error ? N N Int : PCE CRC Error ? Y N Wait for Acknowledge ? Y N(R)=V(S)+1 ? Y N N Wait for Acknowledge ? Y N(R)=V(S)+1 ? Y V(S) = V(S) +1 RESET Wait for Acknowledge Int : ALLS N Set CRCE Response f=1 ? Y RESET Wait for Acknowledge Int :XMR Int : ALLS N V(S) = V(S) +1 RESET Wait for Acknowledge Int : ALLS Data Overflow ? Y Set RDO N N Rec. Ready ? Y Int :RME N Command with p=1 ? Y Rec. Ready ? Y Trm RR Response f=p Trm RNR Response f=p N N(S)=V(R)+1 ? Y Data Overflow ? Y Set RDO N N Int :RME V (R) =V(R)+1 Trm RR Response f=p Int :RME ITD00230 1 Figure 50 Processing of Received Frames in Auto Mode Data Sheet 107 2000-09-14 PEB 20532 PEF 20532 Detailed Protocol Description Transmission of Frames: The SCC autonomously transmits S commands and S responses in the auto mode. Either transparent or I-frames can be transmitted by the user. The software timer has to be operated in the internal timer mode to transmit I-frames. After the frame has been transmitted, the timer is self-started, the XFIFO is inhibited, and the SCC waits for the arrival of a positive acknowledgement. This acknowledgement can be provided by means of an S- or I-frame. If no positive acknowledgement is received during time t1, the SCC transmits an Scommand (p = `1'), which must be answered by an S-response (f = `1'). If the S-response is not received, the process is performed n1 times (in HDLC known as N2, refer to register TIMR3). Upon the arrival of an acknowledgement or after the completion of this poll procedure the XFIFO is enabled and an interrupt is generated. Interrupts may be triggered by the following: * message has been positively acknowledged (ALLS interrupt) * message must be repeated (XMR interrupt) * response has not been received (TIN interrupt). In automode, only when the ALLS interrupt has been issued data of a new frame may be provided to the XFIFO! Upon arrival of an RNR frame, the software timer is started and the status of the remote station is polled periodically after expiration of t1, until the status `receive ready' has been detected. The user is informed via the appropriate interrupt. If no response is received after n1 times, a TIN interrupt, and t1 clock periods thereafter an ALLS interrupt is generated and the process is terminated. Note: The internal timer mode should only be used in the auto mode. Transparent frames can be transmitted in all operating modes. Data Sheet 108 2000-09-14 PEB 20532 PEF 20532 Detailed Protocol Description T Proc. Inactiv 1 Rec. RNR CMDR ; STI Trm I Frame Set wait for Acknowledge Set RRNR Trm RR/RNR Command p=1 Load n1 Load t 1 T Proc. Activ 2 t 1 Run Out Rec. I Frame Rec.RR Rec.RNR n1 = 0 ? N Y RRNR Set ? N Y Response with f=1 ? 2 N Y Load n1 Load t 1 n1 = 7 ? N n1 = n1-1 Int : TIN Load t 1 Y Wait for Acknowledge ? Y N Wait for Acknowledge ? Y N Rec.Ready ? Y Trm RR Command, p=1 N Y N (R) = V (S)+1 ? N Trm RNR Command, p=1 1 2 1 2 ITD00231 11.06.1996 B/R Figure 51 Timer Procedure/Poll Cycle Data Sheet 109 2000-09-14 PEB 20532 PEF 20532 Detailed Protocol Description Examples The interaction between SCC and the host during transmission and reception of I-frames is illustrated in the following two figures. The flow control with RR/RNR of I-frames during transmission/reception is illustrated in Figure 52. Both, the sequence of the poll cycle and protocol errors are shown in Figure 53. I (0.0) ALLS WFA RR(1) Transmit I Frame (RNR) RSC t1 WFA Reception I Frame XMR t1 I (0.0) RNR(0) RNR RME I (0.1) RR(1) RR(0)p=1 RNR(0)f=1 I (1.1) I (1.2) ALLS WFA RR(2) RME Transmit I Frame Confirm with I Frame ALLS RSC(RR) RR(0)p=1 RR(0)f=1 WFA = Wait For Acknowledge (see Status Register) Figure 52 Transmission/Reception of I-Frames and Flow Control Poll Cycle t1 RNR I (0.0) RNR(0) XRNR RR RR(0)p=1 RR(0)f=1 RME I (0.0) RR(1) ALLS PCE WFA Protocol Error I (0.0) RR(0) RR(0)p=1 RR(1) RR(2) RR(0)p=1 RR(0)f=1 ALLS TIN WFA t1 t1 RRp=1 RRp=1 WFA = Wait For Acknowledge (see Status Register) Figure 53 Flow Control: Reception of S-Commands and Protocol Errors Data Sheet 110 2000-09-14 PEB 20532 PEF 20532 Detailed Protocol Description Protocol Error Handling: Depending on the error type, erroneous frames are handled according to Table 14. Table 14 Error Handling Frame Type Error Type I CRC error Aborted Unexpected N(S) Unexpected N(R) CRC error Aborted Unexpected N(R) With I-field Generated Response - - S-frame - - - - - Generated Interrupt RME RME - PCE - - PCE PCE Rec. Status CRC error Abort - - - - - - S Note: The station variables ( V(S), V(R) ) are not changed. 4.6.2 Half-Duplex SDLC-NRM Operation The LAP controllers of the two serial channels can be configured to function in a halfduplex Normal Response Mode (NRM), where they operate as a slave (secondary) station, by setting the NRM bit in the CCR2L register of the corresponding channel. In contrast to the full-duplex LAP B/LAP D operation, where the combined (primary + secondary) station transmits both commands and responses and may transmit data at any time, the NRM mode allows only responses to be transmitted and the secondary station may transmit only when instructed to do so by the master (primary) station. The SCC gets the permission to transmit from the primary station via an S-, or Iframe with the poll bit (p) set. The NRM mode can be profitably used in a point-to-multipoint configuration with a fixed master-slave relationship, which guarantees the absence of collisions on the common transmit line. It is the responsibility of the master station to poll the slaves periodically and to handle error situations. Prerequisite for NRM operation is: - auto mode with 8-bit address field selected Register CCR2L bit fields 'MDS1', 'MDS0', 'ADM' = `000' - Register TIMR3 bit 'TMD' = `0' - same transmit and receive addresses, since only responses can be transmitted, i.e. Register XAD1 = XAD2 and register RAL1 = RAL2 (address of secondary). Data Sheet 111 2000-09-14 PEB 20532 PEF 20532 Detailed Protocol Description Note: The broadcast address may be programmed in register RAL2 if broadcasting is required. In this case registers RAL1 and RAL2 are not equal. The primary station has to operate in transparent HDLC mode. Reception of Frames: The reception of frames functions similarly to the LAPB/LAPD operation (see "FullDuplex LAPB/LAPD Operation" on Page 105). Transmission of Frames: The SCC does not transmit S-, or I-frames if not instructed to do so by the primary station via an S-, or I-frame with the poll bit set. The SCC can be told to send an I-frame issuing the transmit command 'XIF' in register CMDRL. The transmission of the frame, however, will not be initiated by the SCC until reception of either an * RR, or * I-frame with poll bit set (p = `1'). After the frame has been transmitted (with the final bit set), the host has to wait for an ALLS or XMR interrupt. A secondary does not poll the primary for acknowledgements, thus timer supervision must be done by the primary station. Upon the arrival of an acknowledgement the SCC transmit FIFO is enabled and an interrupt is forwarded to the host, either the - message has been positively acknowledged (ALLS interrupt), or the - message must be repeated (XMR interrupt). Additionally, the on-chip timer can be used under host control to provide timer recovery of the secondary if no acknowledgements are received at all. Note: A secondary will transmit transparent frames only if the permission to send is given by receiving an S-frame or I-frame with poll bit set (p = `1'). Examples: A few examples of SCC/host interaction in the case of normal response mode (NRM) mode are shown in Figure 54 and Figure 55. Data Sheet 112 2000-09-14 PEB 20532 PEF 20532 Detailed Protocol Description RR(0)p=1 XIF RME I (0,0)p=1 I(0,1)f=1 RR(0)f=1 I (1,1)p=1 ALLS RR(2)f=1 ITD00237 Secondary ITD01800 Primary Figure 54 No Data to Send: Data Reception/Transmission XIF XIF RR(0)p=1 RR(0)p=1 I (0,0)f=1 I (0,0)f=1 t RR(0)p=1 ALLS RR(1)p=0 XMR RR(0)f=1 ITD00238 ITD01801 Figure 55 Data Transmission (without error), Data Transmission (with error) 4.6.3 Signaling System #7 (SS7) Operation The SEROCCO-M supports the signaling system #7 (SS7) which is described in ITUQ.703. SS7 support must be activated by setting bit 'ESS7' in register CCR3L. Data Sheet 113 2000-09-14 PEB 20532 PEF 20532 Detailed Protocol Description Receive The SS7 protocol is supported by the following hardware features in receive direction: * Recognition of Signaling Unit type * Discard of repeatedly received FISUs and optionally of LSSUs if content is unchanged * Check if the length of the received signaling unit is at least six octets (including the opening flag) * Check if the signal information field of a received signaling unit consists of more than 272 octets (enabled with bit CCR3L.ELC). In this case, reception of the current signaling unit will be aborted. * Counting and processing of errored signaling units In order to reduce the microprocessor load, Fill In Signaling Units (FISUs) are processed automatically. By examining the length indicator of a received Signal Unit (SU) SEROCCO-M decides whether a FISU has been received. Consecutively received FISUs will be compared and not stored in the RFIFO, if the content is equal to the previous one. The same applies to Link Status Signaling Units (LSSUs), if enabled with bit CCR3L.CSF. The different types of Signaling Units as Message Signaling Unit (MSU), Link Status Signaling Unit (LSSU) and Fill-In Signaling Units (FISU) are indicated in the RSTA byte (bit field 'SU'), which is automatically added to the RFIFO with each received Signaling Unit. The complete Signaling Unit except start and end flags is stored in the receive FIFO. The functions of bits CCR3H.RCRC and CCR3H.RADD are also valid in SS7 mode, with bit 'RADD' related to BSN (backward sequence number) and FSN (forward sequence number). Errored signaling units are counted and processed according to ITU-T Q.703. The SU counter and errored-SU counter are reset by setting CMDRH.RSUC to '1'. The error threshold can be selected to be 64 (default) or 32 by clearing/setting bit CCR3L.SUET. If the defined error limit is exceeded, an interrupt (ISR1.SUEX) is generated, if not masked by bit IMR1.SUEX. Transmit In transmit direction, following features are supported: * single or repetitive transmission of signaling units * automatic generation of Fill-In Signaling Units (FISU) Each Signaling Unit (SU) written to the transmit FIFO (XFIFO) will be sent once or repeatedly including flags, CRC checksum and stuffed bits. After e.g. an MSU has been transmitted completely, SEROCCO-M optionally starts sending of Fill In Signaling Units (FISUs) containing the forward sequence number (FSN) and the backward sequence number (BSN) of the previously transmitted signaling unit. Setting bit CCR3L.AFX to '1' causes FISUs to be sent continuously if no Signaling Unit is to be transmitted from XFIFO. After a new signaling unit has been written to the XFIFO and a transmission has been initiated, the current FISU is completed and the new SU is sent. After this, Data Sheet 114 2000-09-14 PEB 20532 PEF 20532 Detailed Protocol Description transmission of FISUs continues. The internally generated FISUs contain FSN and BSN of the last transmitted signaling unit written to XFIFO. Using CMDRL.XREP='1', the contents of XFIFO (1..32 bytes) can be sent continuously. This cyclic transmission can be stopped with the CMDRL.XRES command. Data Sheet 115 2000-09-14 PEB 20532 PEF 20532 Register Description 5 5.1 Register Description Register Overview The SEROCCO-M global registers are used to configure and control the Serial Communication Controllers (SCCs), General Purpose Pins (GPP) and DMA operation. All registers are 8-bit organized registers, but grouped and optimized for 16 bit access. 16 bit access is supported to even addresses only. Table 15 provides an overview about all on-chip registers: Table 15 Offset Ch A 00H 01H 02H 03H 04H 05H 06H 07H 08H 09H 0AH 0BH 0CH 0DH 0EH 0FH 10H 11H 60H 61H B Register Overview Register read write Res Val Meaning Page Global registers: GCMDR GMODE Reserved GSTAR GPDIRL GPDIRH GPDATL GPDATH GPIML GPIMH GPISL GPISH DCMDR Reserved DISR DIMR 00H DMA Interrupt Status Register 77H DMA Interrupt Mask Register Receive/Transmit FIFO (Low Byte) Receive/Transmit FIFO (High Byte) 116 00H Global Command Register 0BH Global Mode Register 00H Global Status Register 07H GPP Direction Register (Low Byte) FFH GPP Direction Register (High Byte) GPP Data Register (Low Byte) GPP Data Register (High Byte) 121 122 124 126 126 128 128 130 130 07H GPP Interrupt Mask Register (Low Byte) FFH GPP Interrupt Mask Register (High Byte) 00H GPP Interrupt Status Register (Low Byte) 132 00H GPP Interrupt Status Register (High Byte) 132 00H DMA Command Register 134 135 137 138 138 2000-09-14 Channel specific registers: RFIFO XFIFO Data Sheet PEB 20532 PEF 20532 Register Description Table 15 Offset Ch A 12H 13H 14H 15H 16H 17H 18H 19H 1AH 1BH 1CH 1DH 1EH 1FH 20H 21H 22H 23H 24H 25H 26H B 62H 63H 64H 65H 66H 67H 68H 69H 6AH 6BH 6CH 6DH 6EH 6FH 70H 71H 72H 73H 74H 75H 76H Register Overview (cont'd) Register read STARL STARH CMDRL CMDRH CCR0L CCR0H CCR1L CCR1H CCR2L CCR2H CCR3L CCR3H PREAMB TOLEN ACCM0 ACCM1 ACCM2 ACCM3 UDAC0 UDAC1 UDAC2 write Res Val Meaning Page 141 141 146 146 151 151 155 155 160 160 167 167 175 176 177 177 178 178 180 180 181 00H Status Register (Low Byte) 10H Status Register (High Byte) 00H Command Register (Low Byte) 00H Command Register (High Byte) 00H Channel Configuration Register 0 (Low Byte) 00H Channel Configuration Register 0 (High Byte) 00H Channel Configuration Register 1 (Low Byte) 00H Channel Configuration Register 1 (High Byte) 00H Channel Configuration Register 2 (Low Byte) 00H Channel Configuration Register 2 (High Byte) 00H Channel Configuration Register 3 (Low Byte) 00H Channel Configuration Register 3 (High Byte) 00H Preamble Register 00H Time Out Length Register 00H PPP ASYNC Control Character Map 0 00H PPP ASYNC Control Character Map 1 00H PPP ASYNC Control Character Map2 00H PPP ASYNC Control Character Map 3 7EH User Defined PPP ASYNC Control Character Map 0 7EH User Defined PPP ASYNC Control Character Map 1 7EH User Defined PPP ASYNC Control Character Map 2 Data Sheet 117 2000-09-14 PEB 20532 PEF 20532 Register Description Table 15 Offset Ch A 27H 28H 29H 2AH 2BH 2CH 2DH 2EH 2FH 30H 31H 32H 33H 34H 35H 36H 37H 38H 39H 3AH 3BH 3CH 3DH 3EH 3FH 40H 41H 42H 43H B 77H 78H 79H 7AH 7BH 7CH 7DH 7EH 7FH 80H 81H 82H 83H 84H 85H 86H 87H 88H 89H 8AH 8BH 8CH 8DH 8EH 8FH 90H 91H 92H 93H Register Overview (cont'd) Register read write UDAC3 TTSA0 TTSA1 TTSA2 TTSA3 RTSA0 RTSA1 RTSA2 RTSA3 PCMTX0 PCMTX1 PCMTX2 PCMTX3 PCMRX0 PCMRX1 PCMRX2 PCMRX3 BRRL BRRH TIMR0 TIMR1 TIMR2 TIMR3 XAD1 XAD2 RAL1 RAH1 RAL2 RAH2 Res Val Meaning Page 181 7EH User Defined PPP ASYNC Control Character Map 3 00H Transmit Time Slot Assignment Register 0 183 00H Transmit Time Slot Assignment Register 1 183 00H Transmit Time Slot Assignment Register 2 184 00H Transmit Time Slot Assignment Register 3 184 00H Receive Time Slot Assignment Register 0 186 00H Receive Time Slot Assignment Register 1 186 00H Receive Time Slot Assignment Register 2 187 00H Receive Time Slot Assignment Register 3 187 00H PCM Mask Transmit Direction Register 0 00H PCM Mask Transmit Direction Register 1 00H PCM Mask Transmit Direction Register 2 00H PCM Mask Transmit Direction Register 3 00H PCM Mask Receive Direction Register 0 00H PCM Mask Receive Direction Register 1 00H PCM Mask Receive Direction Register 2 00H PCM Mask Receive Direction Register 3 00H Baud Rate Register (Low Byte) 00H Baud Rate Register (High Byte) 00H Timer Register 0 00H Timer Register 1 00H Timer Register 2 00H Timer Register 3 00H Transmit Address 1 Register 00H Transmit Address 2 Register 00H Receive Address 1 Low Register 00H Receive Address 1 High Register 00H Receive Address 2 Low Register 00H Receive Address 2 High Register 118 189 189 190 190 192 192 193 193 195 195 197 197 198 198 201 201 203 203 204 204 Data Sheet 2000-09-14 PEB 20532 PEF 20532 Register Description Table 15 Offset Ch A 44H 45H 46H 47H 48H 49H 4AH 4BH 4CH 4DH 4EH 4FH 50H 51H 52H 53H 54H 55H 56H 57H 58H 59H 5AH 5BH B 94H 95H 95H 96H 98H 99H 9AH 9BH 9CH 9DH 9EH 9FH A0H A1H A2H A3H A4H A5H A6H A7H A8H A9H AA H Register Overview (cont'd) Register read write AMRAL1 AMRAH1 AMRAL2 AMRAH2 RLCRL RLCRH XON XOFF MXON MXOFF TCR TICR ISR0 ISR1 ISR2 Reserved IMR0 IMR1 IMR2 Reserved RSTA Reserved SYNCL SYNCH 00H SYN Character Register (Low Byte) 00H SYN Character Register (High Byte) 233 233 00H Receive Status Byte 229 FFH Interrupt Mask Register 0 FFH Interrupt Mask Register 1 03H Interrupt Mask Register 2 226 226 227 Res Val Meaning Page 206 206 207 207 209 209 211 211 00H Mask Receive Address 1 Low Register 00H Mask Receive Address 1 High Register 00H Mask Receive Address 2 Low Register 00H Mask Receive Address 2 High Register 00H Receive Length Check Register (Low Byte) 00H Receive Length Check Register (High Byte) 00H XON In-Band Flow Control Character Register 00H XOFF In-Band Flow Control Character Register 00H XOFF In-Band Flow Control Mask Register 00H Termination Character Register 00H Transmit Immediate Character Register 00H Interrupt Status Register 0 00H Interrupt Status Register 1 00H Interrupt Status Register 2 00H XON In-Band Flow Control Mask Register 213 213 215 216 218 218 219 AB H Data Sheet 119 2000-09-14 PEB 20532 PEF 20532 Register Description Table 15 Offset Ch A 5CH ... 5FH B0H ... B7H B8H B9H BAH ... C3H C4H C5H C6H C7H C8H C9H E4H ... EBH ECH EDH EEH EFH Data Sheet H Register Overview (cont'd) Register read write Res Val Meaning Page B AC Reserved AFH CA H Channel specific DMA registers: Reserved D1H D2H D3H D4H Reserved DD H XBCL XBCH 00H Transmit Byte Count (Low Byte) 00H Transmit Byte Count (High Byte) 236 236 DE H RMBSL RMBSH RBCL RBCH Reserved Reserved 00H Receive Maximum Buffer Size (Low Byte) 238 00H Receive Maximum Buffer Size (High Byte) 238 00H Receive Byte Count (Low Byte) 00H Receive Byte Count (High Byte) 240 240 DF H E0H E1H E2H E3H Miscellaneous: Reserved VER0 VER1 VER2 VER3 03H Version Register 0 E0H Version Register 1 05H Version Register 2 20H Version Register 3 120 242 242 243 243 2000-09-14 PEB 20532 PEF 20532 Register Description 5.2 5.2.1 Detailed Register Description Global Registers Each register description is organized in three parts: * a head with general information about reset value, access type (read/write), offset address and usual handling; * a table containing the bit information (name of bit positions); * a section containing the detailed description of each bit. Register 1 GCMDR Global Command Register CPU Accessibility: Reset Value: Offset Address: typical usage: read/write 00H 00H written by CPU, evaluated by SEROCCO-M Bit 7 6 5 4 3 2 1 0 Global Command Bits 0 0 0 0 0 0 0 SWR SWR Software Reset Command Self clearing command bit: bit='0' bit='1' No software reset command is issued. Causes SEROCCO-M to perform a complete reset identical to hardware reset. Data Sheet 121 2000-09-14 PEB 20532 PEF 20532 Register Description (GMODE) Register 2 GMODE Global Mode Register CPU Accessibility: Reset Value: Offset Address: typical usage: read/write 0BH 01H written by CPU evaluated by SEROCCO-M Bit 7 6 5 4 3 2 1 0 DMA and Global Control 0 EDMA IPC(1:0) OSCPD 0 DSHP GIM EDMA Enable External DMA Support This bit field controls the DMA operation mode: EDMA='0' The external DMA controller support functions are disabled. SEROCCO-M is operated in standard register access controlled mode. External DMA controller support functions are enabled. EDMA='1' IPC(1:0) Interrupt Pin Characteristic These bits control the characteristic of interrupt output pin INT/INT: IPC(1:0) '00' '01' '10' '11' Output Function: Open Drain active low Push/Pull active low Reserved. Push/Pull active high Data Sheet 5-122 2000-09-14 PEB 20532 PEF 20532 Register Description (GMODE) OSCPD Oscillator Power Down Setting this bit to '0' enables the internal oscillator. For power saving purposes (escpecially if clock modes are used which do not need the internal oscillator) this bit may remain set to '1'. OSCPD='0' OSCPD='1' The internal oscillator is active. The internal oscillator is in power down mode. Note: After reset this bit is set to '1', i.e. the oscillator is in power down mode! DSHP Disable Shaper This bit has to be set to '0' if the shaping function in the oscillator unit is desired. The shaper amplifies the oscillator signal and improves the slope of the clock edges. DSHP='0' DSHP='1' Shaper is enabled. Recommended setting if a crystal is connected to pins XTAL1/XTAL2. Shaper is disabled (bypassed). Recommended setting if - a TTL level clock signal is supplied to pin XTAL1 - the oscillator unit is unused Note: After reset this bit is set to '1', i.e. the shaper is disabled! GIM Global Interrupt Mask This bits disables all interrupt indications via pin INT/INT. Internal operation (interrupt generation, interrupt status register update,...) is not affected. If set, pin INT/INT immediately changes or remains in inactive state. GIM='0' Global interrupt mask is cleared. Pin INT/INT is controlled by the internal interrupt control logic and activated as long as at least one unmasked interrupt indication is pending (not yet confirmed by read access to corresponding interrupt status register). Global interrupt mask is set. Pin INT/INT remains inactive. GIM='1' Note: After reset this bit is set to '1', i.e. all interrupts are disabled! Data Sheet 5-123 2000-09-14 PEB 20532 PEF 20532 Register Description (GSTAR) Register 3 GSTAR Global Status Register CPU Accessibility: Reset Value: Offset Address: typical usage: read only 00H 03H written by SEROCCO-M evaluated by CPU Bit 7 6 5 4 3 2 1 0 Global Interrupt Status Information GPI DMI ISA2 ISA1 ISA0 ISB2 ISB1 ISB0 GPI General Purpose Port Indication This bit indicates, that a GPP port interrupt indication is pending: GPI='0' GPI='1' (-) No general purpose port interrupt indication is pending. General purpose port interrupt indication is pending. The source for this interrupt can be further determined by reading registers GPISL/GPISH (refer to page 5-132). (-) DMI DMA Interrupt Indication This bit indicates, that a DMA interrupt indication is pending: DMI='0' DMI='1' No DMA interrupt indication is pending. DMA interrupt indication is pending. The source for this interrupt (channel A/B, receive/transmit) can be further determined by reading register DISR (refer to page 5135). Data Sheet 5-124 2000-09-14 PEB 20532 PEF 20532 Register Description (GSTAR) ISA2 ISA1 ISA0 ISB2 ISB1 ISB0 Channel A Interrupt Status Register 2 Channel A Interrupt Status Register 1 Channel A Interrupt Status Register 0 Channel B Interrupt Status Register 2 Channel B Interrupt Status Register 1 Channel B Interrupt Status Register 0 These bits indicate, that an interrupt indication is pending in the corresponding interrupt status register(s) ISR0/ISR1/ISR2 of the serial communication controller (SCC): bit='0' bit='1' No interrupt indication is pending. An interrupt indication is pending. Data Sheet 5-125 2000-09-14 PEB 20532 PEF 20532 Register Description (GPDIRL) Register 4 GPDIRL GPP Direction Register (Low Byte) CPU Accessibility: Reset Value: Offset Address: typical usage: read/write 07H 04H written by CPU, evaluated by SEROCCO-M Bit 7 6 5 4 3 2 1 0 GPP I/O Direction Control 0 0 0 0 0 GP10DIR GP9DIR GP8DIR Register 5 GPDIRH GPP Direction Register (High Byte) CPU Accessibility: Reset Value: Offset Address: typical usage: read/write FFH 05H written by CPU evaluated by SEROCCO-M Bit 7 6 5 4 3 2 1 0 GPP I/O Direction Control 1 GP6DIR 1 1 1 GP2DIR GP1DIR GP0DIR Data Sheet 5-126 2000-09-14 PEB 20532 PEF 20532 Register Description (GPDIRH) GPnDIR GPP Pin n Direction Control (-) This bit selects between input and output function of the corresponding GPP pin: bit = '0' bit = '1' output input (reset value) Data Sheet 5-127 2000-09-14 PEB 20532 PEF 20532 Register Description (GPDATL) Register 6 GPDATL GPP Data Register (Low Byte) CPU Accessibility: Reset Value: Offset Address: typical usage: read/write 06H written by CPU(outputs) and SEROCCO-M(inputs), evaluated by SEROCCO-M(outputs) and CPU(inputs) Bit 7 6 5 4 3 2 1 0 GPP Data I/O - - - - - GP10DAT GP9DAT GP8DAT Register 7 GPDATH GPP Data Register (High Byte) CPU Accessibility: Reset Value: Offset Address: typical usage: read/write 07H written by CPU(outputs) and SEROCCO-M(inputs), evaluated by SEROCCO-M(outputs) and CPU(inputs) Bit 7 6 5 4 3 2 1 0 GPP Data I/O - GP6DAT - - - GP2DAT GP1DAT GP0DAT Data Sheet 5-128 2000-09-14 PEB 20532 PEF 20532 Register Description (GPDATH) GPnDAT GPP Pin n Data I/O Value This bit indicates the value of the corresponding GPP pin: bit = '0' bit = '1' If direction is input: input level is 'low'; if direction is output: output level is 'low'. If direction is input: input level is 'high'; if direction is output: output level is 'high'. (-) Data Sheet 5-129 2000-09-14 PEB 20532 PEF 20532 Register Description (GPIML) Register 8 GPIML GPP Interrupt Mask Register (Low Byte) CPU Accessibility: Reset Value: Offset Address: typical usage: read/write 07H 08H written by CPU, evaluated by SEROCCO-M Bit 7 6 5 4 3 2 1 0 GPP Interrupt Mask Bits 0 0 0 0 0 GP10IM GP9IM GP8IM Register 9 GPIMH GPP Interrupt Mask Register (High Byte) CPU Accessibility: Reset Value: Offset Address: typical usage: read/write FFH 09H written by CPU, evaluated by SEROCCO-M Bit 7 6 5 4 3 2 1 0 GPP Interrupt Mask Bits 1 GP6IM 1 1 1 GP2IM GP1IM GP0IM Data Sheet 5-130 2000-09-14 PEB 20532 PEF 20532 Register Description (GPIMH) GPnIM GPP Pin n Interrupt Mask This bit controls the interrupt mask of the corresponding GPP pin: bit = '0' (-) Interrupt generation is enabled. An interrupt is generated on any state transition of the corresponding port pin (inputs). Interrupt generation is disabled (reset value). bit = '1' Data Sheet 5-131 2000-09-14 PEB 20532 PEF 20532 Register Description (GPISL) Register 10 GPISL GPP Interrupt Status Register (Low Byte) CPU Accessibility: Reset Value: Offset Address: typical usage: read only 00H 0AH written by SEROCCO-M, read and evaluated by CPU Bit 7 6 5 4 3 2 1 0 GPP Interrupt Status Bits 0 0 0 0 0 GP10I GP9I GP8I Register 11 GPISH GPP Interrupt Status Register (High Byte) CPU Accessibility: Reset Value: Offset Address: typical usage: read only 00H 0BH written by SEROCCO-M, read and evaluated by CPU Bit 7 6 5 4 3 2 1 0 GPP Interrupt Status Bits 0 GP6I 0 0 0 GP2I GP1I GP0I Data Sheet 5-132 2000-09-14 PEB 20532 PEF 20532 Register Description (GPISH) GPnI GPP Pin n Interrupt Indiction (-) This bit indicates if an interrupt event occured on the corresponding GPP pin: bit = '0' bit = '1' No interrupt indication is pending at this pin (no state transition has occured). An interrupt indication is pending (a state transition occured). The interrupt indication is cleared after read access. Data Sheet 5-133 2000-09-14 PEB 20532 PEF 20532 Register Description (DCMDR) Register 12 DCMDR DMA Command Register CPU Accessibility: Reset Value: Offset Address: typical usage: read/write 00H 0CH written by CPU, evaluated by SEROCCO-M Bit 7 6 5 4 3 2 1 0 DMA Controller Reset Command Bits RDTB 0 RDRB 0 RDTA 0 RDRA 0 RDTB RDRB RDTA RDRA Reset DMA Transmit Channel B Reset DMA Receive Channel B Reset DMA Transmit Channel A Reset DMA Receive Channel A Self-clearing command bit. These bits bring the external DMA support logic to the reset state: bit='0' bit='1' No reset is performed. Reset is performed. Data Sheet 5-134 2000-09-14 PEB 20532 PEF 20532 Register Description (DISR) Register 13 DISR DMA Interrupt Status Register CPU Accessibility: Reset Value: Offset Address: typical usage: read only 00H 0EH written by SEROCCO-M, evaluated by CPU Bit 7 6 5 4 3 2 1 0 DMA Interrupt Status Register 0 RBFB RDTEB TDTEB 0 RBFA RDTEA TDTEA Note: Interrupt indications are stored even if masked in register DIMR. Pending interrupts get presented to the system as soon as they get unmasked. RBFB RBFA Receive Buffer Full Channel B Receive Buffer Full Channel A If a receive buffer size is defined in registers RMBSL/RMBSH and during reception the end of the receive buffer is reached this interrupt is generated indicating that the receive buffer is full. If the external DMA controller supports length protection for receive buffers itself this interrupt is obsolete. In that case, the receive buffer length check can be disabled by setting bit RMBSH:DRMBS to '1'. RDTEB RDTEA Receive DMA Transfer End Channel B Receive DMA Transfer End Channel A This bit set to '1' indicates that a DMA transfer of receive data is finished and the receive data is completely moved to the corresponding receive buffer in host memory. Data Sheet 5-135 2000-09-14 PEB 20532 PEF 20532 Register Description (DISR) TDTEB TDTEA Transmit DMA Transfer End Channel B Transmit DMA Transfer End Channel A This bit set to '1' indicates that the data is completely moved from the transmit buffer to the on-chip transmit FIFO, i.e. the transmit byte count programmed in registers XBCL/XBCH is reached. Data Sheet 5-136 2000-09-14 PEB 20532 PEF 20532 Register Description (DIMR) Register 14 DIMR DMA Interrupt Mask Register CPU Accessibility: Reset Value: Offset Address: typical usage: read/write 77H 0FH Bit 7 6 5 4 3 2 1 0 DMA Interrupt Mask Register 0 MRBFB MRDTEB MTDTEB 0 MRBFA MRDTEA MTDTEA MRBFB MRBFA MRDTEB MRDTEA MTDTEB MTDTEA Mask Receive Buffer Full Interrupt Channel B Mask Receive Buffer Full Interrupt Channel A Mask Receive DMA Transfer End Interrupt Channel B Mask Receive DMA Transfer End Interrupt Channel A Mask Transmit DMA Transfer End Interrupt Channel B Mask Transmit DMA Transfer End Interrupt Channel A If a bit in this interrupt mask register is set to '1', the corresponding interrupt is not generated and not indicated in the corresponding bit position in the DISR register. After reset all interrupts are masked. Data Sheet 5-137 2000-09-14 PEB 20532 PEF 20532 Register Description (FIFOL) 5.2.2 Channel Specific SCC Registers Each register description is organized in three parts: * a head with general information about reset value, access type (read/write), channel specific offset addresses and usual handling; * a table containing the bit information (name of bit positions) distinguished for the three major protocol modes HDLC/PPP (H), ASYNC (A) and BISYNC (B); * a section containing the detailed description of each bit; the corresponding modes, the bit is valid for, are marked again by a bracket term right beside the full bit name. Register 15 CPU Accessibility: Reset Value: Offset Address: typical usage: FIFOL Receive/Transmit FIFO (Low Byte) read/write Channel A 10H Channel B 60H XFIFO: written by CPU, evaluated by SEROCCO-M RFIFO: written by SEROCCO-M, evaluated by CPU Bit 7 6 5 4 3 2 1 0 RFIFO/XFIFO Access Low Byte FIFO(7:0) Register 16 CPU Accessibility: Reset Value: Offset Address: typical usage: FIFOH Receive/Transmit FIFO (High Byte) read/write Channel A 11H Channel B 61H XFIFO: written by CPU, evaluated by SEROCCO-M RFIFO: written by SEROCCO-M, evaluated by CPU Bit 7 6 5 4 3 2 1 0 RFIFO/XFIFO Access High Byte FIFO(15:8) Data Sheet 5-138 2000-09-14 PEB 20532 PEF 20532 Register Description (FIFOH) Receive FIFO (RFIFO) Reading data from the RFIFO can be done in 8-bit (byte) or 16-bit (word) accesses, depending on the selected microprocessor bus width using signal 'WIDTH'. In 16-bit bus mode only 16-bit accesses to RFIFO are allowed. Only for a frame with odd byte count the last access can be an 8-bit access. The size of the accessible part of RFIFO is determined by programming the RFIFO threshold level in bit field CCR3H.RFTH(1:0). If the HDLC/PPP protocol machine is selected, the threshold can be adjusted to 32 (reset value), 16, 4 or 2 bytes. With the ASYNC and BISYNC protocol machines following threshold levels can be selected: 1 (reset value), 4, 16 or 32 bytes. * Interrupt Controlled Data Transfer (GMODE.EDMA='0') Up to 32 bytes/16 words of received data can be read from the RFIFO following an RPF or an RME interrupt (see ISR0 register). The address provided during an RFIFO read access is not incremental; it is always 10H for channel A or 60H for channel B. RPF Interrupt: This interrupt indicates that the adjusted receive threshold level is reached. The message is not yet complete. A fix number of bytes, dependent from the threshold level, has to be read. RME Interrupt: The message is completely received. The number of valid bytes is determined by reading the RBCL, RBCH registers. The content of the RFIFO is released by issuing the "Receive Message Complete" command (CMDRH.RMC). * DMA Controlled Data Transfer (GMODE.EDMA='1') If DMA operation is enabled, the SEROCCO-M autonomously requests data transfer by asserting the DRR line to the external DMA controller. The DRR line remains active until the beginning of the last receive data byte/word transfer. For a detailed decsription of the external DMA interface operation refer to "External DMA Controller Support" on Page 79. Transmit FIFO (XFIFO) Writing data to the XFIFO can be done in 8-bit (byte) or 16-bit (word) accesses, depending on the selected microprocessor bus width using signal 'WIDTH'. In 16-bit bus mode only 16-bit accesses to XFIFO are allowed. Only for a frame with odd byte count the last access must be an 8-bit access. * Interrupt Controlled Data Transfer (GMODE.EDMA='0') Following an XPR (or an ALLS) interrupt, up to 32 bytes/16 words of new transmit data can be written into the XFIFO. Transmit data can be released for transmission with an XTF command. The address provided during an XFIFO write access is not incremental; it is always 10H for channel A or 60H for channel B. * DMA Controlled Data Transfer (GMODE.EDMA='1') Data Sheet 5-139 2000-09-14 PEB 20532 PEF 20532 Register Description (FIFOH) If DMA operation is enabled, the SEROCCO-M autonomously requests data transfer to the XFIFO by asserting the DRT line to the external DMA controller. The DRT line remains active until the beginning of the last transmit data byte/word transfer. For a detailed description of the external DMA interface operation refer to "External DMA Controller Support" on Page 79. Data Sheet 5-140 2000-09-14 PEB 20532 PEF 20532 Register Description (STARL) Register 17 CPU Accessibility: Reset Value: Offset Address: typical usage: STARL Status Register (Low Byte) read only 00H Channel A 12H Channel B 62H updated by SEROCCO-M read and evaluated by CPU Bit Mode 7 6 5 4 3 2 1 0 Command Status Transmitter Status H A B XREPE XREPE XREPE 0 0 0 0 TEC 0 CEC CEC CEC 0 FCS 0 XDOV XDOV XDOV XFW XFW XFW CTS CTS CTS Register 18 CPU Accessibility: Reset Value: Offset Address: typical usage: STARH Status Register (High Byte) read only 10H Channel A 13H Channel B 63H updated by SEROCCO-M read and evaluated by CPU Bit Mode 7 6 5 Receiver Status 4 3 2 1 Automode Status 0 H A B 0 0 0 0 RFNE RFNE CD CD CD RLI 0 SYNC DPLA DPLA DPLA WFA 0 0 XRNR 0 0 RRNR 0 0 Data Sheet 5-141 2000-09-14 PEB 20532 PEF 20532 Register Description (STARH) XREPE Transmit Repetition Executing XREPE='0' XREPE='1' (all modes) No transmit repetition command is in execution. A XREP command (register CMDRL) is currently in execution. (async mode) TEC TIC Executing TIC='0' No TIC (transmit immediate character) is currently in transmission. Access to register TICR is allowed to initiate a TIC transmission. A TIC command (write access to register TICR) is accepted but not completely executed. No further write access to register TICR is allowed until 'TIC' bit is cleared by SEROCCO-M. (all modes) TIC='1' CEC Command Executing CEC='0' CEC='1' No command is currently in execution. The command registers CMDRL/CMDRH can be written by CPU. A command (written previously to registers CMDRL/ CMDRH) is currently in execution. No further command can be written to registers CMDRL/CMDRH by CPU. Note: CEC will stay active if the SCC is in power-down mode or if no serial clock, needed for command execution, is available. FCS Flow Control Status (async mode) If (in-band) flow control mechanism is enabled via bit 'FLON' in register CCR2H this bit indicates the current state of transmitter: FCS='0' FCS='1' Transmitter is ready (always after transmitter reset command or XON-character detected). Transmitter is stopped (XOFF-character detected). Data Sheet 5-142 2000-09-14 PEB 20532 PEF 20532 Register Description (STARH) XDOV Transmit FIFO Data Overflow XDOV='0' XDOV='1' (all modes) Less than or equal to 32 bytes have been written to the XFIFO. More than 32 bytes have been written to the XFIFO. This bit is reset by: - a transmitter reset command 'XRES' - or when all bytes in the accessible half of the XFIFO have been moved into the inaccessible half. (all modes) XFW Transmit FIFO Write Enable XFW='0' XFW='1' The XFIFO is not able to accept further transmit data. Transmit data can be written to the XFIFO. (all modes) CTS CTS (Clear To Send) Input Signal State CTS='0' CTS='1' CTS input signal is inactive (high level) CTS input signal is active (low level) Note: A transmit clock is necessary to detect the input level of CTS. Optionally this input can be programmed to generate an interrupt on signal level changes. RFNE Receive FIFO Not Empty (async/bisync modes) This status bit is set if the SCC receive FIFO (RFIFO) holds at least one valid byte. RFNE='0' RFNE='1' CD The receive FIFO is empty. The receive FIFO is not empty. (all modes) CD (Carrier Detect) Input Signal State This status bit gives the signal state of CD input. This bit value is independent of the programmed polarity of the Carrier Detect function (bit 'ICD' in register CCR1H). CD='0' CD='1' CD input signal is low. CD input signal is high. Note: Optionally this input can be programmed to generate an interrupt on signal level changes. Data Sheet 5-143 2000-09-14 PEB 20532 PEF 20532 Register Description (STARH) SYNC Synchronization Status (bisync mode) This bit indicates whether the receiver is in synchronized state. After a 'HUNT' command 'SYNC' bit is cleared and the receiver starts searching for a SYNC character. When found the 'SYNC' status bit is set immediately, an SCD-interrupt is generated (if enabled) and receive data is forwarded to the receiver FIFO. SYNC='0' Synchronization is lost or not yet achieved. (after reset or after new 'HUNT' command has been issued and before SYNC character is found) The receiver is in synchronized state. (hdlc mode) SYNC='1' RLI Receive Line Inactive This bit indicates that neither flags as interframe time fill nor data are being received via the receive line. RLI='0' RLI='1' Receive line is active, no constant high level is detected. Receive line is inactive, i.e. more than 7 consecutive '1' are detected on the line. Note: A receive clock must be provided in order to detect the receive line state. DPLA DPLL Asynchronous (all modes) This bit is only valid if the receive clock is recovered by the DPLL and FM0, FM1 or Manchester data encoding is selected. It is set when the DPLL has lost synchronization. In this case reception is disabled (receive abort condition) until synchronization has been regained. In addition transmission is interrupted in all cases where transmit clock is derived from the DPLL (clock mode 3a, 7a). Interruption of transmission is performed the same way as on deactivation of the CTS signal. DPLA='0' DPLA='1' DPLL is synchronized. DPLL is asynchronous (re-synchronization process is started automatically). Data Sheet 5-144 2000-09-14 PEB 20532 PEF 20532 Register Description (STARH) WFA Wait For Acknowledgement (hdlc mode) This status bit is significant in Automode only. It indicates whether the Automode state machine expects an acknowledging I- or S-Frame for a previously sent I-Frame. WFA='0' WFA='1' No acknowledge I/S-Frame is expected. The Automode state machine is waiting for an achnowledging S- or I-Frame. (hdlc mode) XRNR Transmit RNR Status This status bit is significant in Automode only. It indicates the receiver status of the local station (SCC). XRNR='0' XRNR='1' The receiver is ready and will automatically answer pollframes with a S-Frame with 'receiver-ready' indication. The receiver is NOT ready and will automatically answer poll-frames with a S-Frame with a 'receiver-not-ready' indication. (hdlc mode) RRNR Received RNR (Receiver Not Ready) Status This status bit is significant in Automode only. It indicates the receiver status of the remote station. RRNR='0' RRNR='1' The remote station receiver is ready. The remote receiver is NOT ready. (A 'receiver-not-ready' indication was received from the remote station) Data Sheet 5-145 2000-09-14 PEB 20532 PEF 20532 Register Description (CMDRL) Register 19 CPU Accessibility: Reset Value: Offset Address: typical usage: CMDRL Command Register (Low Byte) read/write 00H Channel A 14H Channel B 64H written by CPU, evaluated by SEROCCO-M Bit Mode 7 Timer 6 5 4 3 2 1 0 Transmitter Commands H A B STI STI STI TRES TRES TRES XIF TXON 0 XRES XRES XRES XF XF XF XME XME XME XREP XREP XREP 0 TXOFF 0 Register 20 CPU Accessibility: Reset Value: Offset Address: typical usage: CMDRH Command Register (High Byte) read/write 00H Channel A 15H Channel B 65H written by CPU, evaluated by SEROCCO-M Bit Mode 7 6 5 4 3 2 1 0 Receiver Commands H A B RMC RMC RMC RNR 0 0 0 0 0 0 0 0 RSUC 0 HUNT 0 0 0 0 RFRD RFRD RRES RRES RRES The command register contains self-clearing command bits. The command bits read a '1' until the corresponding command is executed completely. Data Sheet 5-146 2000-09-14 PEB 20532 PEF 20532 Register Description (CMDRH) For a write access to the register, the new value gets OR'ed with the current register contents. The 'CEC' bit in register STARL/STARH is the OR-function over all command bits. STI Start Timer Command (all modes) Self-clearing command bit: HDLC Automode: In HDLC Automode the timer is used internally for the autonomous protocol support functions. The timer is started automatically by the SCC when an I-Frame is sent out and needs to be acknowledged. If the 'STI' command is issued by software: STI='1' An S-Frame with poll bit set is sent out and the internal timer is started expecting an acknowledge from the remote station via an I- or S-Frame. The timer is stopped after receiving an acknowledge otherwise the timer expires generating a timer interrupt. Note: In HDLC Automode, bit 'TMD' in register TIMR3 must be set to '1' All protocol modes except HDLC Automode: In these modes the timer is operating as a general purpose timer. STI='1' This commands starts timer operation. The timer can be stopped by setting bit 'TRES'. Note: Bit 'TMD' in register TIMR3 must be cleared for proper operation TRES Timer Reset Self-clearing command bit. This bit deactivates timer operation: TRES='0' TRES='1' XIF Timer operation enabled. Timer operation stopped. (hdlc mode) (all modes) Transmit I-Frame Self-clearing command bit. This command bit is significant in HDLC Automode only. XIF='1' Initiates the transmission of an I-frame in auto-mode. Additional to the opening flag, the address and control fields of the frame are added by SEROCCO-M. Data Sheet 5-147 2000-09-14 PEB 20532 PEF 20532 Register Description (CMDRH) TXOFF Transmit Off Command (async mode) Self-clearing command bit: This command bit is significant if in-band flow-control is selected. TXOFF='1' Forces the transmitter to enter its 'transmit off' state. This is equal to receiving an XOFF character. (async mode) TXON Transmit On Command Self-clearing command bit: This command bit is significant if in-band flow-control is selected. TXON='1' Forces the transmitter to enter its 'transmit on' state. This is equal to receiving an XON character. (all modes) XRES Transmitter Reset Command Self-clearing command bit: XRES='1' The SCC transmit FIFO is cleared and the transmitter protocol engines are reset to their initial state. A transmitter reset command is recommended after all changes in protocol mode configurations (e.g. switching between the protocol engines HDLC/ASYNC/BISYNC or sub-modes of HDLC). (all modes) XF Transmit Frame This self-clearing command bit is significant in interrupt driven operation only (GMODE.EDMA='0'). XF='1' After having written up to 32 bytes to the XFIFO, this command initiates transmission. In packet oriented protocols like HDLC/PPP the opening flag is automatically added by SEROCCO-M. If the end of the packet is part of the transmit data, bit 'XME' should be set in addition. DMA Mode After having written the length of the data block to be transmitted to registers XBCL and XBCH, this command initiates the data transfer from host memory to SEROCCO-M by DMA. Transmission on the serial side starts as soon as 32 bytes are transferred to the XFIFO or the transmit byte counter value is reached. Data Sheet 5-148 2000-09-14 PEB 20532 PEF 20532 Register Description (CMDRH) XME Transmit Message End Self-clearing command bit: XME='1' Indicates that the data block written last to the XFIFO contains the end of the packet. This bit should always be set in conjunction with a transmit command ('XF' or 'XIF'). (hdlc mode) (hdlc/bisync modes) XREP Transmission Repeat Command Self-clearing command bit: XREP='1' If bit 'XREP' is set together with bit 'XME' and 'XF', SEROCCO-M repeatedly transmits the contents of the XFIFO (1..32 bytes). The cyclic transmission can be stopped with the 'XRES' command. (all modes) RMC Receive Message Complete Self-clearing command bit: RMC='1' With this bit the CPU indicates to SEROCCO-M that the current receive data has been fetched out of the RFIFO. Thus the corresponding space in the RFIFO can be released and re-used by SEROCCO-M for further incoming data. (hdlc mode) RNR Receiver Not Ready Command NON self-clearing command bit: This command bit is significant in HDLC Automode only. RNR='0' Forces the receiver to enter its 'receiver-ready' state. The receiver acknowledges received poll or I-Frames with a 'receiver-ready' indication. Forces the receiver to enter its 'receiver-not-ready' state. The receiver acknowledges received poll or I-Frames with a 'receiver-not-ready' indication. (hdlc mode) RNR='1' RSUC Reset Signaling Unit Counter Self-clearing command bit: This command bit is significant if HDLC SS7 mode is selected. RSUC='1' The Signaling System #7 (SS7) unit counter is reset. Data Sheet 5-149 2000-09-14 PEB 20532 PEF 20532 Register Description (CMDRH) HUNT Enter Hunt State Command Self-clearing command bit: HUNT='1' This command forces the receiver to enter its 'HUNT' state immediately. Thus synchronization is 'lost' and the receiver starts searching for new SYNC characters. (async/bisync modes) (bisync mode) RFRD Receive FIFO Read Enable Command Self-clearing command bit: RFRD='1' This command forces insertion of a 'block end' condition into the RFIFO before the receive FIFO threshold is exceeded or a block end condition (termination character detected or time-out) is fulfilled. The execution of this command is reported with a TCD interrupt. (all modes) RRES Receiver Reset Command Self-clearing command bit: RRES='1' The SCC receive FIFO is cleared and the receiver protocol engines are reset to their initial state. The SCC receive FIFO accepts new receive data from the protocol engine immediately after receiver reset procedure. It is recommended to disable data reception before issuing a receiver reset command by setting bit CCR3L.RAC = '0' and enabling data reception afterwards. A 'receiver reset' command is recommended after all changes in protocol mode configurations (switching between the protocol engines HDLC/ASYNC/BISYNC or sub-modes of HDLC). Data Sheet 5-150 2000-09-14 PEB 20532 PEF 20532 Register Description (CCR0L) Register 21 CPU Accessibility: Reset Value: Offset Address: typical usage: CCR0L Channel Configuration Register 0 (Low Byte) read/write 00H Channel A 16H Channel B 66H written by CPU; read and evaluated by SEROCCO-M Bit Mode 7 6 misc. 5 4 3 2 1 0 Clock Mode Selection H A B VIS VIS VIS PSD PSD PSD BCR BCR 0 TOE TOE TOE SSEL SSEL SSEL CM(2:0) CM(2:0) CM(2:0) Register 22 CPU Accessibility: Reset Value: Offset Address: typical usage: CCR0H Channel Configuration Register 0 (High Byte) read/write 00H Channel A 17H Channel B 67H written by CPU; read and evaluated by SEROCCO-M Bit Mode 7 Power 6 5 Line Coding 4 3 2 1 0 Protocol Mode H A B PU PU PU SC(2:0) SC(2:0) SC(2:0) 0 0 0 0 0 0 SM(1:0) SM(1:0) SM(1:0) Data Sheet 5-151 2000-09-14 PEB 20532 PEF 20532 Register Description (CCR0H) VIS Masked Interrupts Visible VIS='0' VIS='1' (all modes) Masked interrupt status bits are not displayed in the interrupt status registers (ISR0..ISR2). Masked interrupt status bits are visible and automatically cleared after interrupt status register (ISR0..ISR2) read access. Note: Interrupts masked in registers IMR0..IMR2 will not generate an interrupt. PSD DPLL Phase Shift Disable (all modes) This option is only applicable in the case of NRZ or NRZI line encoding is selected. PSD='0' PSD='1' Normal DPLL operation. The phase shift function of the DPLL is disabled. The windows for phase adjustment are extended. (async PPP, ASYNC modes) BCR Bit Clock Rate This bit is only valid in asynchronous PPP and ASYNC protocol mode and only in clock modes not using the DPLL (0, 1, 3b, 7b). It is also invalid in clock mode 4. BCR='0' BCR='1' Selects isochronous operation with bit clock rate 1. Data bits are sampled once. Selects standard asynchronous operation with bit clock rate 16. Using 16 samples per bit, data bits are sampled 3 times around the nominal bit center. The resulting bit value is determined by majority decision of the 3 samples. For correct operation NRZ data encoding has to be selected. Data Sheet 5-152 2000-09-14 PEB 20532 PEF 20532 Register Description (CCR0H) TOE Transmit Clock Out Enable (all modes) For clock modes 0b, 2b, 3a, 3b, 6b, 7a and 7b, the internal transmit clock can be monitored on pin TxCLK as an output signal. In clock mode 5, a time slot control signal marking the active transmit time slot is output on pin TxCLK. Bit 'TOE' is invalid for all other clock modes. TOE='0' TOE='1' TxCLK pin is input. TxCLK pin is switched to output function if applicable for the selected clock mode. (all modes) SSEL Clock Source Select Distinguishes between the 'a' and 'b' option of clock modes 0, 2, 3, 5, 6 and 7. SSEL='0' SSEL='1' CM(2:0) Clock Mode Option 'a' is selected. Option 'b' is selected. (all modes) This bit field selects one of main clock modes 0..7. For a detailed description of the clock modes refer to Chapter 3.2.3 CM = '000' CM = '001' CM = '010' CM = '011' CM = '100' CM = '101' CM = '110' CM = '111' PU Power Up PU='0' clock mode 0 clock mode 1 clock mode 2 clock mode 3 clock mode 4 clock mode 5 (time-slot oriented clocking modes) clock mode 6 clock mode 7 (all modes) The SCC is in 'power-down' mode. The protocol engines are switched off (standby) and no operation is performed. This may be used to save power when SCC is not in use. Note: The SCC transmit FIFO accepts transmit data even in 'power-down' mode. PU='1' The SCC is in 'power-up' mode. Data Sheet 5-153 2000-09-14 PEB 20532 PEF 20532 Register Description (CCR0H) SC(2:0) Serial Port Configuration (all modes) This bit field selects the line coding of the serial port. Note, that special operation modes and settings may require or exclude operation in special line coding modes. Refer to the 'prerequisites' in the dedicated mode descriptions. SC = '000' SC = '001' SC = '010' SC = '011' SC = '100' SC = '101' SC = '110' SC = '111' NRZ data encoding Bus configuration, timing mode 1 (NRZ data encoding) NRZI data encoding Bus configuration, timing mode 2 (NRZ data encoding) FM0 data encoding FM1 data encoding Manchester data encoding Reserved Note: If bus configuration mode is selected, only NRZ data encoding is supported. SM(1:0) Serial Port Mode (all modes) This bit field selects one of the three protocol engines. Depending on the selected protocol engine the SCC related registers change or special bit positions within the registers change their meaning. SM = '00' SM = '01' SM = '10' SM = '11' HDLC/PPP protocol engine Reserved (do not use) BISYNC protocol engine ASYNC protocol engine Data Sheet 5-154 2000-09-14 PEB 20532 PEF 20532 Register Description (CCR1L) Register 23 CPU Accessibility: Reset Value: Offset Address: typical usage: CCR1L Channel Configuration Register 1 (Low Byte) read/write 00H Channel A 18H Channel B 68H written by CPU; read and evaluated by SEROCCO-M Bit Mode 7 6 5 4 misc. 3 2 1 0 H A B CRL 0 0 C32 0 0 0 0 SOC(1:0) 0 0 SFLG 0 0 DIV DIV DIV ODS ODS ODS 0 0 0 Register 24 CPU Accessibility: Reset Value: Offset Address: typical usage: CCR1H Channel Configuration Register 1 (High Byte) read/write 00H Channel A 19H Channel B 69H written by CPU; read and evaluated by SEROCCO-M Bit Mode 7 6 5 4 misc. 3 2 1 0 H A B 0 0 0 ICD ICD ICD 0 0 0 RTS RTS RTS FRTS FRTS FRTS FCTS FCTS FCTS CAS CAS CAS TSCM TSCM TSCM Data Sheet 5-155 2000-09-14 PEB 20532 PEF 20532 Register Description (CCR1H) CRL CRC Reset Value (hdlc mode) This bit defines the initial value of the internal transmit/receive CRC generators: CRL='0' Initial value is 0xFFFFH (16 bit CRC), 0xFFFFFFFFH (32 bit CRC). This is the default value for most HDLC/PPP applications. Initial value is 0x0000H (16 bit CRC), 0x00000000H (32 bit CRC). (hdlc mode) CRL='1' C32 CRC 32 Select C32='0' C32='1' This bit enables 32-bit CRC operation for transmit and receive. 16-bit CRC-CCITT generation/checking. 32-bit CRC generation/checking. Note: The internal 'valid frame' criteria is updated depending on the selected number of CRC-bytes. SOC(1:0) Serial Output Control (hdlc mode) This bit field selects the RTS signal output function. (This bit field is only valid in bus configuration modes selected via bit field SC(2:0) in register CCR0H). SOC = '0X' SOC = '10' SOC = '11' RTS ouput signal is active during transmission of a frame (active low). RTS ouput signal is always inactive (high). RTS ouput signal is active during reception of a frame (active low). (hdlc mode) SFLG Shared Flags Transmission This bit enables 'shared flag transmission' in HDLC protocol mode. If another transmit frame begin is stored in the SCC transmit FIFO, the closing flag of the preceding frame becomes the opening flag of the next frame (shared flags): SFLG = '0' SFLG = '1' Shared flag transmission disabled. Shared flag transmission enabled. Note: The receiver always supports shared flags and shared zeros of consecutive flags. Data Sheet 5-156 2000-09-14 PEB 20532 PEF 20532 Register Description (CCR1H) DIV Data Inversion (all modes) This bit is only valid if NRZ data encoding is selected via bit field SC(2:0) in register CCR0H. DIV='0' DIV='1' No Data Inversion. Data is transmitted/received inverted (on a per bit basis). In HDLC and HDLC Synchronous PPP modes the continuous '1' idle sequence is NOT inverted. Thus it is recommended to select the flag sequence for interframe time fill transmission (CCR2H:ITF = '1'), which is inverted. (all modes) ODS Output Driver Select The transmit data output pin TxD can be configured as push/pull or open drain output chracteristic. ODS='0' ODS='1' ICD TxD pin is open drain output. TxD pin is push/pull output. (all modes) Invert Carrier Detect Pin Polarity ICD='0' ICD='1' Carrier Detect (CD) input pin is active high. Carrier Detect (CD) input pin is active low. RTS Request To Send Pin Control (all modes) The request to send pin RTS can be controlled by SEROCCO-M as an output autonomously or via setting/clearing bit 'RTS'. This bit is not valid in clock mode 4. RTS='0' Pin RTS (output) pin is controlled by SEROCCO-M autonomously. HDLC Mode: RTS is activated during transmission. In bus configuration mode the functionality depends on bit field 'SOC' setting. Note: For autonomous RTS pin control a transmit clock is necessary. ASYNC/BISYNC Mode: The functionality depends on setting of bit 'FRTS' RTS='1' Pin RTS can be controlled by software. The output level of this pin depends on bit 'FRTS'. Data Sheet 5-157 2000-09-14 PEB 20532 PEF 20532 Register Description (CCR1H) FRTS Flow Control (using signal RTS) RTS, FRTS 0, 0 Pin RTS is controlled by SEROCCO-M autonomously. RTS is activated (low) as soon as transmit data is available within the SCC transmit FIFO. Pin RTS is controlled by SEROCCO-M autonomously supporting bi-directional data flow control. RTS is activated (low) if the shadow part of the SCC receive FIFO is empty and de-activated (high) when the SCC receive FIFO fill level reaches its receive FIFO threshold. Forces pin RTS to active state (low). Forces pin RTS to inactive state (high). (all modes) (all modes) Bit 'FRTS' together with bit 'RTS' determine the function of signal RTS: 0, 1 1, 1, FCTS 0 1 Flow Control (using signal CTS) This bit controls the function of pin CTS. FCTS = '0' The transmitter is stopped if CTS input signal is inactive (high) and enabled if active (low). Note: In the character oriented protocol modes (ASYNC, BISYNC, asynchronous PPP), the current byte is completely sent even if CTS becomes inactive during transmission. FCTS = '1' The transmitter is enabled, disregarding CTS input signal. Data Sheet 5-158 2000-09-14 PEB 20532 PEF 20532 Register Description (CCR1H) CAS Carrier Detect Auto Start CAS = '0' (all modes) The CD pin is used as general input. In clock mode 1, 4 and 5, clock mode specific control signals must be provided at this pin (receive strobe, receive gating RCG, frame sync clock FSC). A pull-up/down resistor is recommended if unused. The CD pin enables/disables the receiver for data reception. (Polarity of CD pin can be configured via bit 'ICD'.) CAS = '1' Note: (1) In clock mode 1, 4 and 5 this bit must be set to '0'. (2) A receive clock must be provided for the autonomous receiver control function of the CD input pin. (3) In ASYNC mode the transmitter is additionally controlled by inband flow control mechanism (if enabled). TSCM Time Slot Control Mode (all modes) This bit controls internal counter operation in time slot oriented clock mode 5: TSCM='0' TSCM='1' The internal counter keeps running, restarting with zero after being expired. The internal counter stops at its maximum value and restarts with the next frame sync pulse again. Data Sheet 5-159 2000-09-14 PEB 20532 PEF 20532 Register Description (CCR2L) Register 25 CPU Accessibility: Reset Value: Offset Address: typical usage: CCR2L Channel Configuration Register 2 (Low Byte) read/write 00H Channel A 1AH Channel B 6AH written by CPU; read and evaluated by SEROCCO-M Bit Mode 7 6 5 4 misc. 3 2 1 0 H A B 0 0 MDS(1:0) 0 0 ADM 0 0 NRM 0 0 PPPM(1:0) 0 SLEN 0 BISNC TLPO TLPO TLPO TLP TLP TLP Register 26 CPU Accessibility: Reset Value: Offset Address: typical usage: CCR2H Channel Configuration Register 2 (High Byte) read/write 00H Channel A 1BH Channel B 6BH written by CPU; read and evaluated by SEROCCO-M Bit Mode 7 6 5 4 misc. 3 2 1 0 H A B MCS 0 0 EPT 0 EPT NPRE(1:0) 0 0 ITF 0 ITF 0 0 0 OIN 0 CAPP XCRC FLON CRCM NPRE(1:0) Data Sheet 5-160 2000-09-14 PEB 20532 PEF 20532 Register Description (CCR2H) MDS(1:0) Mode Select (hdlc modes) This bit field selects the HDLC protocol sub-mode including the 'extended transparent mode'. MDS = '00' MDS = '01' MDS = '10' MDS = '11' Automode. Address Mode 2. Address Mode 0/1. (Option '0' or '1' is selected via bit 'ADM'.) Extended transparent mode (bit transparent transmission/ reception). Note: 'MDS(1:0)' must be set to '10' if any PPP mode is enabled via bit field 'PPPM' or if SS7 is enabled via bit 'ESS7' in register CCR3L. ADM Address Mode Select Automode, Address Mode 2: Determines the address field length of an HDLC frame. ADM = '0' ADM = '1' 8-bit address field. 16-bit address field. (hdlc modes) The meaning of this bit depends on the selected protocol sub-mode: Address Mode 0/1: Determines whether address mode 0 or 1 is selected. ADM = '0' ADM = '1' ADM = '1' NRM Address Mode 0 (no address recognition). Address Mode 1 (high byte address recognition). recommended setting (hdlc modes) Extended Transparent Mode: Normal Response Mode This bit is valid in HDLC Automode operation only and determines the function of the Automode LAP-Controller: NRM = '0' NRM = '1' Full-duplex LAP-B / LAP-D operation. Half-duplex normal response mode (NRM) operation. Data Sheet 5-161 2000-09-14 PEB 20532 PEF 20532 Register Description (CCR2H) PPPM(1:0) PPP Mode Select (hdlc modes) This bit field enables and selects the HDLC PPP protocol modes: PPPM = '00' No PPP protocol operation. The HDLC sub-mode is determined by bit field 'MDS'. PPPM = '01' Octet synchronous PPP protocol operation. PPPM = '10' Asynchronous PPP protocol operation. Bit 'BCR' in register CCR0L must be set to ensure proper asynchronous reception. PPPM = '11' Bit synchronous PPP protocol operation. Note: 'Address Mode 0' must be selected by setting bit field 'MDS(1:0)' to '10' and bit 'ADM' to '0' if any PPP mode is enabled. TLPO Test Loop Out Function (all modes) This bit is only valid if test loop is enabled and controls whether test loop transmit data is driven on pin TxD: TLPO = '0' TLPO = '1' Test loop transmit data is driven to TxD pin. Test loop transmit data is NOT driven to TxD pin. TxD pin is idle '1'. Depending on the selected output characteristic the pin is high impedance (bit CCR1L.ODS ='0') or driving high (CCR1L.ODS ='1'). (all modes) TLP Test Loop This bit controls the internal test loop between transmit and receive data signals. The test loop is closed at the far end of serial transmit and receive line just before the respective TxD and RxD pins: TLP = '0' TLP = '1' Test loop disabled. Test loop enabled. The software is responsible to select a clock mode which allows correct reception of transmit data depending on the external clock supply. Transmit data is sent out via pin TxD if not disabled with bit 'TLPO'. The receive input pin RxD is internally disconnected during test loop operation. Data Sheet 5-162 2000-09-14 PEB 20532 PEF 20532 Register Description (CCR2H) SLEN SYNC Character Length (bisync mode) This bit selects the SYNC character length in BISYNC/MONOSYNC operation mode: SLEN = '0' SLEN = '1' BISNC 6 bit (MONOSYNC), 12 bit (BISYNC). 8 bit (MONOSYNC), 16 bit (BISYNC). (bisync mode) Select MONOSYNC/BISYNC Mode BISNC = '0' BISNC = '1' MONOSYNC mode. BISYNC mode. This bit selects BISYNC or MONOSYNC operation mode: MCS Modulo Count Select (hdlc modes) This bit is valid in HDLC Automode operation only and determines the control field format: MCS = '0' MCS = '1' Basic operation, one byte control field (modulo 8 counter operation). Extended operation, two bytes control field (modulo 128 counter operation). (hdlc/bisync mode) EPT Enable Preamble Transmission This bit enables preamble transmission. The preamble is started after interframe time fill (ITF) transmission is stopped because a new frame is ready to be transmitted. The preamble pattern consists of 8 bits defined in register PREAMB, which is sent repetitively. The number of repetitions is determined by bit field 'PRE(1:0)': EPT='0' EPT='1' Preamble transmission is disabled. Preamble transmission is enabled. Note: Preamble operation does NOT influence HDLC shared flag transmission if enabled. Data Sheet 5-163 2000-09-14 PEB 20532 PEF 20532 Register Description (CCR2H) NPRE(1:0) Number of Preamble Repetitions NPRE = '00' 1 preamble. NPRE = '01' 2 preambles. NPRE = '10' 4 preambles. NPRE = '11' 8 preambles. ITF Interframe Time Fill ITF='0' ITF='1' (hdlc/bisync mode) (hdlc/bisync mode) This bit field determines the number of preambles transmitted: This bit selects the idle state of the transmit pin TxD: Continuous logical '1' is sent during idle phase. HDLC Mode: Continuous flag sequences are sent ('01111110' flag pattern). BISYNC Mode: Continuous SYN characters are output. Note: It is recommended to clear bit 'ITF' in bus configuration modes, i.e. continuous '1's are sent as idle sequence and data encoding is NRZ. OIN One Insertion (hdlc mode) In HDLC mode a one-insertion mechanism similar to the zero-insertion can be activated: OIN='0' OIN='1' The '1' insertion mechanism is disabled. In transmit direction a logical '1' is inserted to the serial data stream after 7 consecutive zeros. In receive direction a '1' is deleted from the receive data stream after receiving 7 consecutive zeros. This enables clock information to be recovered from the receive data stream by means of a DPLL, even in the case of NRZ data encoding, because a transition at bit cell boundary occurs at least every 7 bits. Data Sheet 5-164 2000-09-14 PEB 20532 PEF 20532 Register Description (CCR2H) XCRC Transmit CRC Checking Mode XCRC='0' XCRC='1' (hdlc mode) The transmit checksum (2 or 4 bytes) is generated and appended to the transmit data automatically. The transmit checksum is not generated automatically. The checksum is expected to be provided by software as the last 2 or 4 bytes in the transmit data buffer. (async mode) FLON Flow Control Enable In ASYNC mode, in-band flow control is supported: FLON='0' No automatic in-band flow-control is performed. However recognition of a flow control character (XON/XOFF) causes always a maskable interrupt event. Automatic in-band flow-control is performed. Reception of a XOFF character (defined in register XNXF) turns off the transmitter after the currently transmitted character has been shifted out completely (XOFF state). Reception of a XON character (defined in register XNXF) resumes the transmitter from XOFF into XON state ready to send available transmit data bytes. The current flow control state is indicated via bit 'FCS' in register Star. Any transmitter reset switches the flow-control logic to XON state. (bisync mode) No CRC generation/checking is active in BISYNC mode. The CRC generator is activated: 1. The CRC generator is initialized every time the transmission of a new 'frame' starts. The CRC initialization value can be selected via bit 'CRL' in register CCR2 (for BISYNC operation). 2. The CRC is automatically to the last transmitted data of a 'frame'. FLON='1' CAPP CRC Append In BISYNC mode the CRC generator can be activated: CAPP = '0' CAPP = '1' Data Sheet 5-165 2000-09-14 PEB 20532 PEF 20532 Register Description (CCR2H) CRCM CRC Mode Select (bisync mode) In BISYNC mode the CRC generator can be configured for two different generator polynoms: CRCM = '0' CRCM = '1' CRC-16: The polynominal is x16+x15+x2+1. CRC-CCITT: The polynominal is x16+x15+x5+1. Data Sheet 5-166 2000-09-14 PEB 20532 PEF 20532 Register Description (CCR3L) Register 27 CPU Accessibility: Reset Value: Offset Address: typical usage: CCR3L Channel Configuration Register 3 (Low Byte) read/write 00H Channel A 1CH Channel B 6CH written by CPU; read and evaluated by SEROCCO-M Bit Mode 7 6 5 4 misc. 3 2 1 0 H A B ELC TCDE TCDE AFX 0 SLOAD CSF SUET RAC RAC RAC 0 DXS 0 0 XBRK 0 ESS7 STOP STOP CHL(1:0) CHL(1:0) Register 28 CPU Accessibility: Reset Value: Offset Address: typical usage: CCR3H Channel Configuration Register 3 (High Byte) read/write 00H Channel A 1DH Channel B 6DH written by CPU; read and evaluated by SEROCCO-M Bit Mode 7 6 5 4 misc. 3 2 1 0 H A B 0 DRCRC PAR(1:0) PAR(1:0) RCRC PARE PARE RADD DPS DPS 0 RFDF RFDF 0 0 0 RFTH(1:0) RFTH(1:0) RFTH(1:0) Data Sheet 5-167 2000-09-14 PEB 20532 PEF 20532 Register Description (CCR3H) ELC Enable Length Check (hdlc mode) This bit is only valid in HDLC SS7 mode: If the number of received octets exceeds 272 + 7 within one Signaling Unit, reception is aborted and bit RSTA.RAB is set. ELC='0' ELC='1' TCDE Length Check disabled. Length Check enabled. (async/bisync modes) Termination Character Detection Enable This bit is valid in ASYNC/BISYNC modes only and enables/disables the termination character detection mechanism: TCDE = '0' TCDE = '1' No receive termination character detection is performed. The termination character detection is enabled. The receive data stream is monitored for the occurence of a termination character (TC) programmed via register TCR. When this character is detected, a 'TCD' interrupt is generated to the CPU (unless masked). Note: If the programmed character length (bit field 'CHL(1:0)') is less than 8 bits, the most significant unused bits in register TCR must be set to '0'. Otherwise no termination character will be detected. AFX Automatic FISU Transmission (hdlc mode) This bit is only valid in HDLC SS7 mode: After the contents of the transmit FIFO (XFIFO) has been transmitted completely, FISUs are transmited automatically. These FISUs contain the FSN and BSN of the last transmitted Signaling Unit (provided in XFIFO). AFX='0' AFX='1' Automatic FISU transmission disabled. Automatic FISU transmission enabled. Data Sheet 5-168 2000-09-14 PEB 20532 PEF 20532 Register Description (CCR3H) SLOAD Enable SYN Character Load (bisync mode) In BISYNC mode, SYN characters might be filtered out or stored to the SCC receive FIFO. SLOAD='0' SLOAD='1' SYN characters are filtered out and not stored in the receive FIFO. All received characters, including SYN characters, are stored in the receive FIFO. (hdlc mode) CSF Compare Status Field This bit is only valid in HDLC SS7 mode: If the status fields of consecutive LSSUs are equal, only the first will be stored and every following is ignored CSF='0' CSF='1' Compare is disabled, all received LSSUs are stored in the receive FIFO. Compare is enabled, only the first one of consecutive equal LSSUs is stored in the receive FIFO. (hdlc mode) SUET Signalling Unit Counter Threshold This bit is only valid in HDLC SS7 mode: Defines the number of signaling units received in error that will cause an error rate high indication (ISR1.SUEX). SUET='0' SUET='1' CHL(1:0) threshold is 64 errored signaling units. threshold is 32 errored signaling units. (async/bisync modes) Character Length CHL = '00' CHL = '01' CHL = '10' CHL = '11' 8-bit data. 7-bit data. 6-bit data. 5-bit data. This bit field selects the number of data bits within a character: RAC Receiver active RAC='0' RAC='1' Receiver inactive, receive line is ignored. (all modes) Switches the receiver between operational/inoperational states: Receiver active. Data Sheet 5-169 2000-09-14 PEB 20532 PEF 20532 Register Description (CCR3H) DXS Disable Storage of XON/XOFF Characters (async mode) In ASYNC mode, XON/XOFF characters might be filtered out or stored to the SCC receive FIFO: DXS='0' DXS='1' All received characters including XON/XOFF characters are stored in the receive FIFO. XON/XOFF characters are filtered out and not stored in the receive FIFO. (async mode) XBRK Transmit Break XBRK='0' XBRK='1' Normal transmit operation. Forces the TxD pin to 'low' level immediately (break condition), regardless of any character being currently transmitted. This command is executed immediately with the next rising edge of the transmit clock and further transmission is disabled. The currently sent character is lost. Data stored in the SCC transmit FIFO will be sent as soon as the break condition is cleared (XBRK='0'). A transmit reset command (bit 'XRES' in register CMDRL) does NOT clear the break condition automatically. (hdlc mode) ESS7 Enable SS7 Mode This bit is only valid in HDLC mode only. ESS7='0' ESS7='1' Disable signaling system #7 (SS7) support. Enable signaling system #7 (SS7) support. Note: If SS7 mode is enabled, 'Address Mode 0' must be selected by setting bit field CCR2L:MDS(1:0) to '10' and bit CCR2L:ADM to '0'. STOP Stop Bit number STOP='0' STOP='1' 1 stop bit per character. 2 stop bits per character. (async mode) This bit selects the number of stop bits per ASYNC character: Data Sheet 5-170 2000-09-14 PEB 20532 PEF 20532 Register Description (CCR3H) PAR(1:0) Parity Format PAR = '00' PAR = '01' PAR = '10' PAR = '11' (async/bisync modes) This bit field selects the parity generation/checking mode: SPACE ('0'), a constant '0' is inserted as parity bit. Odd parity. Even parity. MARK ('1'), a constant '1' is inserted as parity bit. The received parity bit is stored in the SCC receive FIFO depending on the selected character format: * as leading bit immediately preceding the data bits if character length is 5, 6 or 7 bits and bit 'DPS' is cleared ('0'). * as LSB of the status byte belonging to the character if character length is 8 bits and the corresponding receive FIFO data format is selected (bit 'RFDF' = '1'). A parity error is indicated in the MSB of the status byte belonging to each character if enabled. In addition, a parity error interrupt can be generated. DRCRC Disable Receive CRC Checking DRCRC='0' (hdlc mode) The receiver expects a 16 or 32 bit CRC within a HDLC frame. CRC processing depends on the setting of bit 'RCRC'. Frames shorter than expected are marked 'invalid' or are discarded (refer to RSTA description). The receiver does not expect any CRC within a HDLC frame. The criteria for 'valid frame' indication is updated accordingly (refer to RSTA description). Bit 'RCRC' is ignored. (hdlc mode) DRCRC='1' RCRC Receive CRC Checking Mode RCRC='0' RCRC='1' The received checksum is evaluated, but NOT forwarded to the receive FIFO. The received checksum (2 or 4 bytes) is evaluated and forwarded to the receive FIFO as data. (async/bisync modes) PARE Parity Enable PARE='0' PARE='1' Parity generation/checking is disabled. Parity generation/checking is enabled. 5-171 2000-09-14 Data Sheet PEB 20532 PEF 20532 Register Description (CCR3H) RADD Receive Address Forward to RFIFO (hdlc mode) This bit is only valid - if an HDLC sub-mode with address field support is selected (Automode, Address Mode 2, Address Mode 1) - in SS7 mode RADD='0' The received HDLC address field (either 8 or 16 bit, depending on bit 'ADM') is evaluated, but NOT forwarded to the receive FIFO. In SS7 mode, the signaling unit fields 'FSN' and 'BSN' are NOT forwarded to the receive FIFO. The received HDLC address field (either 8 or 16 bit, depending on bit 'ADM') is evaluated and forwarded to the receive FIFO. In SS7 mode, the signaling unit fields 'FSN' and 'BSN' are forwarded to the receive FIFO. (async/bisync modes) RADD='1' DPS Data Parity Storage DPS='0' DPS='1' The parity bit is stored. Only valid if parity generation/checking is enabled via bit 'PARE': The parity bit is not stored in the data byte containing character data. The parity bit is always stored in the status byte. Data Sheet 5-172 2000-09-14 PEB 20532 PEF 20532 Register Description (CCR3H) RFDF Receive FIFO Data Format (async/bisync mode) In ASYNC mode, the character format is determined as follows: RFDF='0' Data Byte: 7 5 4 0 RFDF='1' Data Byte (DB): 7 5 4 0 Status Byte (SB): 7 6 0 P P 7 6 5 Char5 0 7 6 P 5 Char5 0 PE FE 7 6 0 P 0 P 0 P P 7 6 Char6 0 7 P 6 Char6 0 PE FE 7 6 P 7 Char7 0 P 7 Char7 0 PE FE 7 6 Char8 (no parity bit stored) Char8 (no parity bit stored) PE FE P: Parity bit stored in data byte (can be disabled via bit 'DPS') PE: Parity Error FE: Frame Error P: Parity bit stored in status byte Data Sheet 5-173 2000-09-14 PEB 20532 PEF 20532 Register Description (CCR3H) RFTH(1:0) Receive FIFO Threshold (all modes) This bit field defines the level up to which the SCC receive FIFO is filled with valid data before an 'RPF' interrupt is generated. (In case of a 'frame end / block end' condition the SEROCCO-M notifies the CPU immediately, disregarding this threshold.) The meaning depends on the selected protocol engine: HDLC Modes: RFTH(1:0) '00' '01' '10' '11' RFTH(1:0) Threshold level in number of data bytes. 32 byte 16 byte 4 byte 2 byte Threshold level in number of data bytes (DB) and status bytes (SB) depending on bit 'RFDF': RFDF = '0' RFDF = '1' 1 DB 4 DB 16 DB 32 DB 1 DB + 1 SB 2 DB + 2 SB 8 DB + 8 SB 16 DB + 16 SB ASYNC/BISYNC Mode: '00' '01' '10' '11' Data Sheet 5-174 2000-09-14 PEB 20532 PEF 20532 Register Description (PREAMB) Register 29 CPU Accessibility: Reset Value: Offset Address: typical usage: PREAMB Preamble Register read/write 00H Channel A 1EH Channel B 6EH written by CPU; read and evaluated by SEROCCO-M Bit Mode 7 6 5 4 3 2 1 0 Preamble Pattern H A B 0 0 0 0 PRE(7:0) 0 PRE(7:0) 0 0 0 PRE(7:0) Preamble (hdlc/bisync modes) This bit field determines the preamble pattern which is send out during preamble transmission. Note: In HDLC-mode, zero-bit insertion is disabled during preamble transmission. Data Sheet 5-175 2000-09-14 PEB 20532 PEF 20532 Register Description (TOLEN) Register 30 CPU Accessibility: Reset Value: Offset Address: typical usage: TOLEN Time Out Length Register read/write 00H Channel A 1FH Channel B 6FH written by CPU; read and evaluated by SEROCCO-M Bit Mode 7 6 5 4 3 2 1 0 Time Out Length H A B 0 TOIE 0 0 0 0 0 TOLEN(6:0) 0 0 0 0 0 0 0 0 0 0 TOIE Time Out Indication Enable (async mode) If this bit is set to '1' in ASYNC mode, any time out event will automatically generate an 'RFRD' command thus inserting a 'block end' indication into the RFIFO. This time-out condition is indicated with the 'TIME' interrupt (if unmasked). TOIE = '0' TOIE = '1' Automatic Time Out processing disabled. Automatic Time Out processing enabled. (async mode) TOLEN(6:0) Time Out Length This bit field determines the time out period. If there is no receive line activity for the configured period of time, a time out indication is generated if enabled via bit 'TOIE'. The period of time is programmable in multiples of character frame length Data Sheet 5-176 2000-09-14 PEB 20532 PEF 20532 Register Description (ACCM0) Register 31 CPU Accessibility: Reset Value: Offset Address: typical usage: ACCM0 PPP ASYNC Control Character Map 0 read/write 00H Channel A 20H Channel B 70H written by CPU; read and evaluated by SEROCCO-M Bit Mode 7 6 5 4 3 2 1 0 ASYNC Character Control Map 07..00 H A B 07 0 0 06 0 0 05 0 0 04 0 0 03 0 0 02 0 0 01 0 0 00 0 0 Register 32 CPU Accessibility: Reset Value: Offset Address: typical usage: ACCM1 PPP ASYNC Control Character Map 1 read/write 00H Channel A 21H Channel B 71H written by CPU; read and evaluated by SEROCCO-M Bit Mode 7 6 5 4 3 2 1 0 ASYNC Character Control Map 0F..08 H A B 0F 0 0 0E 0 0 0D 0 0 0C 0 0 0B 0 0 0A 0 0 09 0 0 08 0 0 Data Sheet 5-177 2000-09-14 PEB 20532 PEF 20532 Register Description (ACCM2) Register 33 CPU Accessibility: Reset Value: Offset Address: typical usage: ACCM2 PPP ASYNC Control Character Map2 read/write 00H Channel A 22H Channel B 72H written by CPU; read and evaluated by SEROCCO-M Bit Mode 7 6 5 4 3 2 1 0 ASYNC Character Control Map 17..10 H A B 17 0 0 16 0 0 15 0 0 14 0 0 13 0 0 12 0 0 11 0 0 10 0 0 Register 34 CPU Accessibility: Reset Value: Offset Address: typical usage: ACCM3 PPP ASYNC Control Character Map 3 read/write 00H Channel A 23H Channel B 73H written by CPU; read and evaluated by SEROCCO-M Bit Mode 7 6 5 4 3 2 1 0 ASYNC Character Control Map 1F..18 H A B 1F 0 0 1E 0 0 1D 0 0 1C 0 0 1B 0 0 1A 0 0 19 0 0 18 0 0 Data Sheet 5-178 2000-09-14 PEB 20532 PEF 20532 Register Description (ACCM3) ACCM ASYNC Character Control Map (hdlc modes) This bit field is valid in HDLC asynchronous and octet-synchronous PPP mode only: Each bit selects the corresponding character (indicated as hex value 1FH..00H in the register description table) as control character which has to be mapped into the transmit data stream. Data Sheet 5-179 2000-09-14 PEB 20532 PEF 20532 Register Description (UDAC0) Register 35 CPU Accessibility: Reset Value: Offset Address: typical usage: UDAC0 User Defined PPP ASYNC Control Character Map 0 read/write 7EH Channel A 24H Channel B 74H written by CPU; read and evaluated by SEROCCO-M Bit Mode 7 6 5 4 3 2 1 0 ASYNC Character 0 H A B 0 0 0 0 0 0 0 0 AC0 0 0 0 0 0 0 0 0 Register 36 CPU Accessibility: Reset Value: Offset Address: typical usage: UDAC1 User Defined PPP ASYNC Control Character Map 1 read/write 7EH Channel A 25H Channel B 75H written by CPU; read and evaluated by SEROCCO-M Bit Mode 7 6 5 4 3 2 1 0 ASYNC Character 1 H A B 0 0 0 0 0 0 0 0 AC1 0 0 0 0 0 0 0 0 Data Sheet 5-180 2000-09-14 PEB 20532 PEF 20532 Register Description (UDAC2) Register 37 CPU Accessibility: Reset Value: Offset Address: typical usage: UDAC2 User Defined PPP ASYNC Control Character Map 2 read/write 7EH Channel A 26H Channel B 76H written by CPU; read and evaluated by SEROCCO-M Bit Mode 7 6 5 4 3 2 1 0 ASYNC Character 2 H A B 0 0 0 0 0 0 0 0 AC2 0 0 0 0 0 0 0 0 Register 38 CPU Accessibility: Reset Value: Offset Address: typical usage: UDAC3 User Defined PPP ASYNC Control Character Map 3 read/write 7EH Channel A 27H Channel B 77H written by CPU; read and evaluated by SEROCCO-M Bit Mode 7 6 5 4 3 2 1 0 ASYNC Character 3 H A B 0 0 0 0 0 0 0 0 AC3 0 0 0 0 0 0 0 0 Data Sheet 5-181 2000-09-14 PEB 20532 PEF 20532 Register Description (UDAC3) AC3..0 User Defined ASYNC Character Control Map (hdlc mode) This bit field is valid in HDLC asynchronous and octet-synchronous PPP mode only: These bit fields define user determined characters as control characters which have to be mapped into the transmit data stream. In register ACCM only characters 00H..1FH can be selected as control characters. Register UDAC allows to specify any four characters in the range 00H..FFH . The default value is a 7EH flag which must be always mapped. Thus no additional character is mapped if 7EH 's are programed to bit fields AC3...0 (reset value). (7EH is mapped automatically, even if not defined via a AC bit field.) Data Sheet 5-182 2000-09-14 PEB 20532 PEF 20532 Register Description (TTSA0) Register 39 CPU Accessibility: Reset Value: Offset Address: typical usage: TTSA0 Transmit Time Slot Assignment Register 0 read/write 00H Channel A 28H Channel B 78H written by CPU; read and evaluated by SEROCCO-M Bit Mode 7 6 5 4 3 2 1 0 Tx Clock Shift 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 H A B TCS(2:0) TCS(2:0) TCS(2:0) Register 40 CPU Accessibility: Reset Value: Offset Address: typical usage: TTSA1 Transmit Time Slot Assignment Register 1 read/write 00H Channel A 29H Channel B 79H written by CPU; read and evaluated by SEROCCO-M Bit Mode 7 6 5 4 3 2 1 0 Tx Time Slot Number H A B TEPCM TEPCM TEPCM TTSN(6:0) TTSN(6:0) TTSN(6:0) Data Sheet 5-183 2000-09-14 PEB 20532 PEF 20532 Register Description (TTSA2) Register 41 CPU Accessibility: Reset Value: Offset Address: typical usage: TTSA2 Transmit Time Slot Assignment Register 2 read/write 00H Channel A 2AH Channel B 7AH written by CPU; read and evaluated by SEROCCO-M Bit Mode 7 6 5 4 3 2 1 0 Transmit Channel Capacity TCC(7:0) TCC(7:0) TCC(7:0) H A B Register 42 CPU Accessibility: Reset Value: Offset Address: typical usage: TTSA3 Transmit Time Slot Assignment Register 3 read/write 00H Channel A 2BH Channel B 7BH written by CPU; read and evaluated by SEROCCO-M Bit Mode 7 6 5 4 3 2 1 0 Transmit Channel Capacity 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TCC8 TCC8 TCC8 H A B Data Sheet 5-184 2000-09-14 PEB 20532 PEF 20532 Register Description (TTSA3) The following register bit fields allow flexible assignment of bit- or octet-aligned transmit time-slots to the serial channel. For more detailed information refer to chapters "Clock Mode 5a (Time Slot Mode)" on Page 55 and "Clock Mode 5b (Octet Sync Mode)" on Page 62. TCS(2:0) Transmit Clock Shift This bit field determines the transmit clock shift. TEPCM Enable PCM Mask Transmit (all modes) (all modes) This bit selects the additional Transmit PCM Mask (refer to register PCMTX0..PCMTX3): TEPCM='0' TEPCM='1' Standard time-slot configuration. The time-slot width is constant 8 bit, bit fields 'TTSN' and 'TCS' determine the offset of the PCM mask and 'TCC' is ignored. Each time-slot selected via register PCMTX0..PCMTX3 is an active transmit timeslot. (all modes) TTSN(6:0) Transmit Time Slot Number This bit field selects the start position of the timeslot in time-slot configuration mode (clock mode 5a/5b): Offset = 1+TTSN*8 + TCS (1..1024 clocks) TCC(8:0) Transmit Channel Capacity (all modes) This bit field determines the transmit time-slot width in standard time-slot configuration (bit TEPCM='0'): Number of bits = TCC + 1, (1..512 bits/time-slot) Data Sheet 5-185 2000-09-14 PEB 20532 PEF 20532 Register Description (RTSA0) Register 43 CPU Accessibility: Reset Value: Offset Address: typical usage: RTSA0 Receive Time Slot Assignment Register 0 read/write 00H Channel A 2CH Channel B 7CH written by CPU; read and evaluated by SEROCCO-M Bit Mode 7 6 5 4 3 2 1 0 Rx Clock Shift 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 H A B RCS(2:0) RCS(2:0) RCS(2:0) Register 44 CPU Accessibility: Reset Value: Offset Address: typical usage: RTSA1 Receive Time Slot Assignment Register 1 read/write 00H Channel A 2DH Channel B 7DH written by CPU; read and evaluated by SEROCCO-M Bit Mode 7 6 5 4 3 2 1 0 Rx Time Slot Number H A B REPCM REPCM REPCM RTSN(6:0) RTSN(6:0) RTSN(6:0) Data Sheet 5-186 2000-09-14 PEB 20532 PEF 20532 Register Description (RTSA2) Register 45 CPU Accessibility: Reset Value: Offset Address: typical usage: RTSA2 Receive Time Slot Assignment Register 2 read/write 00H Channel A 2EH Channel B 7EH written by CPU; read and evaluated by SEROCCO-M Bit Mode 7 6 5 4 3 2 1 0 Receive Channel Capacity RCC(7:0) RCC(7:0) RCC(7:0) H A B Register 46 CPU Accessibility: Reset Value: Offset Address: typical usage: RTSA3 Receive Time Slot Assignment Register 3 read/write 00H Channel A 2FH Channel B 7FH written by CPU; read and evaluated by SEROCCO-M Bit Mode 7 6 5 4 3 2 1 0 Receive Channel Capacity 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RCC8 RCC8 RCC8 H A B Data Sheet 5-187 2000-09-14 PEB 20532 PEF 20532 Register Description (RTSA3) The following register bit fields allow flexible assignment of bit- or octet-aligned receive time-slots to the serial channel. For more detailed information refer to chapters "Clock Mode 5a (Time Slot Mode)" on Page 55 and "Clock Mode 5b (Octet Sync Mode)" on Page 62. RCS(2:0) Receive Clock Shift This bit field determines the receive clock shift. REPCM Enable PCM Mask Receive (all modes) (all modes) This bit selects the additional Receive PCM Mask (refer to register PCMRX0..PCMRX3): REPCM='0' REPCM='1' Standard time-slot configuration. The time-slot width is constant 8 bit, bit fields 'RTSN' and 'RCS' determine the offset of the PCM mask and 'RCC' is ignored. Each time-slot selected via register PCMRX0..PCMRX3 is an active receive timeslot. (all modes) RTSN(6:0) Receive Time Slot Number This bit field selects the start position of the timeslot in time-slot configuration mode (clock mode 5a/5b): Offset = 1+RTSN*8 + RCS (1..1024 clocks) RCC(8:0) Receive Channel Capacity (all modes) This bit field determines the receive time-slot width in standard time-slot configuration (bit REPCM='0'): Number of bits = RCC + 1, (1..512 bits/time-slot) Data Sheet 5-188 2000-09-14 PEB 20532 PEF 20532 Register Description (PCMTX0) Register 47 CPU Accessibility: Reset Value: Offset Address: typical usage: PCMTX0 PCM Mask Transmit Direction Register 0 read/write 00H Channel A 30H Channel B 80H written by CPU; read and evaluated by SEROCCO-M Bit Mode 7 6 5 4 3 2 1 0 PCM Mask for Transmit Direction H A B T07 T07 T07 T06 T06 T06 T05 T05 T05 T04 T04 T04 T03 T03 T03 T02 T02 T02 T01 T01 T01 T00 T00 T00 Register 48 CPU Accessibility: Reset Value: Offset Address: typical usage: PCMTX1 PCM Mask Transmit Direction Register 1 read/write 00H Channel A 31H Channel B 81H written by CPU; read and evaluated by SEROCCO-M Bit Mode 7 6 5 4 3 2 1 0 PCM Mask for Transmit Direction H A B T15 T15 T15 T14 T14 T14 T13 T13 T13 T12 T12 T12 T11 T11 T11 T10 T10 T10 T09 T09 T09 T08 T08 T08 Data Sheet 5-189 2000-09-14 PEB 20532 PEF 20532 Register Description (PCMTX2) Register 49 CPU Accessibility: Reset Value: Offset Address: typical usage: PCMTX2 PCM Mask Transmit Direction Register 2 read/write 00H Channel A 32H Channel B 82H written by CPU; read and evaluated by SEROCCO-M Bit Mode 7 6 5 4 3 2 1 0 PCM Mask for Transmit Direction H A B T23 T23 T23 T22 T22 T22 T21 T21 T21 T20 T20 T20 T19 T19 T19 T18 T18 T18 T17 T17 T17 T16 T16 T16 Register 50 CPU Accessibility: Reset Value: Offset Address: typical usage: PCMTX3 PCM Mask Transmit Direction Register 3 read/write 00H Channel A 33H Channel B 83H written by CPU; read and evaluated by SEROCCO-M Bit Mode 15 14 13 12 11 10 9 8 PCM Mask for Transmit Direction H A B T31 T31 T31 T30 T30 T30 T29 T29 T29 T28 T28 T28 T27 T27 T27 T26 T26 T26 T25 T25 T25 T24 T24 T24 Data Sheet 5-190 2000-09-14 PEB 20532 PEF 20532 Register Description (PCMTX3) PCMTX PCM Mask for Transmit Direction (all mode) This bit field is valid in clock mode 5 only and the PCM mask must be enabled via bit 'TEPCM' in register TTSA1. Each bit selects one of 32 (8-bit) transmit time-slots. The offset of timeslot zero to the frame sync pulse can be programmed via register TTSA1 bit field 'TTSN'. Data Sheet 5-191 2000-09-14 PEB 20532 PEF 20532 Register Description (PCMRX0) Register 51 CPU Accessibility: Reset Value: Offset Address: typical usage: PCMRX0 PCM Mask Receive Direction Register 0 read/write 00H Channel A 34H Channel B 84H written by CPU; read and evaluated by SEROCCO-M Bit Mode 7 6 5 4 3 2 1 0 PCM Mask for Receive Direction H A B R07 R07 R07 R06 R06 R06 R05 R05 R05 R04 R04 R04 R03 R03 R03 R02 R02 R02 R01 R01 R01 R00 R00 R00 Register 52 CPU Accessibility: Reset Value: Offset Address: typical usage: PCMRX1 PCM Mask Receive Direction Register 1 read/write 00H Channel A 35H Channel B 85H written by CPU; read and evaluated by SEROCCO-M Bit Mode 15 14 13 12 11 10 9 8 PCM Mask for Receive Direction H A B R15 R15 R15 R14 R14 R14 R13 R13 R13 R12 R12 R12 R11 R11 R11 R10 R10 R10 R09 R09 R09 R08 R08 R08 Data Sheet 5-192 2000-09-14 PEB 20532 PEF 20532 Register Description (PCMRX2) Register 53 CPU Accessibility: Reset Value: Offset Address: typical usage: PCMRX2 PCM Mask Receive Direction Register 2 read/write 00H Channel A 36H Channel B 86H written by CPU; read and evaluated by SEROCCO-M Bit Mode 7 6 5 4 3 2 1 0 PCM Mask for Receive Direction H A B R23 R23 R23 R22 R22 R22 R21 R21 R21 R20 R20 R20 R19 R19 R19 R18 R18 R18 R17 R17 R17 R16 R16 R16 Register 54 CPU Accessibility: Reset Value: Offset Address: typical usage: PCMRX3 PCM Mask Receive Direction Register 3 read/write 00H Channel A 37H Channel B 87H written by CPU; read and evaluated by SEROCCO-M Bit Mode 15 14 13 12 11 10 9 8 PCM Mask for Receive Direction H A B R31 R31 R31 R30 R30 R30 R29 R29 R29 R28 R28 R28 R27 R27 R27 R26 R26 R26 R25 R25 R25 R24 R24 R24 Data Sheet 5-193 2000-09-14 PEB 20532 PEF 20532 Register Description (PCMRX3) PCMRX PCM Mask for Receive Direction (all mode) This bit field is valid in clock mode 5 only and the PCM mask must be enabled via bit 'REPCM' in register RTSA1. Each bit selects one of 32 (8-bit) receive time-slots. The offset of timeslot zero to the frame sync pulse can be programmed via register RTSA1 bit field 'RTSN'. Data Sheet 5-194 2000-09-14 PEB 20532 PEF 20532 Register Description (BRRL) Register 55 CPU Accessibility: Reset Value: Offset Address: typical usage: BRRL Baud Rate Register (Low Byte) read/write 00H Channel A 38H Channel B 88H written by CPU; read and evaluated by SEROCCO-M Bit Mode 7 6 5 4 3 2 1 0 Baud Rate Generator Factor N H A B 0 0 0 0 0 0 BRN(5:0) BRN(5:0) BRN(5:0) Register 56 CPU Accessibility: Reset Value: Offset Address: typical usage: BRRH Baud Rate Register (High Byte) read/write 00H Channel A 39H Channel B 89H written by CPU; read and evaluated by SEROCCO-M Bit Mode 7 6 5 4 3 2 1 0 Baud Rate Generator Factor M H A B 0 0 0 0 0 0 0 0 0 0 0 0 BRM(3:0) BRM(3:0) BRM(3:0) Data Sheet 5-195 2000-09-14 PEB 20532 PEF 20532 Register Description (BRRH) BRM(3:0) BRN(5:0) Baud Rate Factor 'M' Baud Rate Factor 'N' (all modes) (all modes) These bit fields determine the division factor of the internal baud rate generator. The baud rate generator input clock and the usage of baud rate generator output depends on the selected clock mode. The division factor k is calculated by: k = ( N + 1) 2M with M=0..15 and N=0..63. f BRG = f in k Data Sheet 5-196 2000-09-14 PEB 20532 PEF 20532 Register Description (TIMR0) Register 57 CPU Accessibility: Reset Value: Offset Address: typical usage: TIMR0 Timer Register 0 read/write 00H Channel A 3AH Channel B 8AH written by CPU; read and evaluated by SEROCCO-M Bit Mode 7 6 5 4 3 2 1 0 Timer Value H A B Register 58 CPU Accessibility: Reset Value: Offset Address: typical usage: TIMR1 Timer Register 1 read/write 00H Channel A 3BH TVALUE(7:0) TVALUE(7:0) TVALUE(7:0) Channel B 8BH written by CPU; read and evaluated by SEROCCO-M Bit Mode 7 6 5 4 3 2 1 0 Timer Value H A B TVALUE(15:0) TVALUE(15:0) TVALUE(15:0) Data Sheet 5-197 2000-09-14 PEB 20532 PEF 20532 Register Description (TIMR2) Register 59 CPU Accessibility: Reset Value: Offset Address: typical usage: TIMR2 Timer Register 2 read/write 00H Channel A 3CH Channel B 8CH written by CPU; read and evaluated by SEROCCO-M Bit Mode 7 6 5 4 3 2 1 0 Timer Value H A B Register 60 CPU Accessibility: Reset Value: Offset Address: typical usage: TIMR3 Timer Register 3 read/write 00H Channel A 3DH TVALUE(23:16) TVALUE(23:16) TVALUE(23:16) Channel B 8DH written by CPU; read and evaluated by SEROCCO-M Bit Mode 7 6 5 4 3 2 1 0 Timer Configuration H A B SRC SRC SRC 0 0 0 0 0 0 TMD 0 0 0 0 0 CNT(2:0) CNT(2:0) CNT(2:0) Data Sheet 5-198 2000-09-14 PEB 20532 PEF 20532 Register Description (TIMR3) SRC Clock Source (valid in clock mode 5 only) This bit selects the clock source of the internal timer: SRC = '0' SRC = '1' (all modes) The timer is clocked by the effective transmit clock. The timer is clocked by the frame-sync synchronization signal supplied via the FSC pin in clock mode 5. (hdlc modes) TMD Timer Mode This bit must be set to '1' if HDLC Automode operation is selected. In all other protocol modes it must remain '0': TMD='0' The timer is controlled by the CPU via access to registers CMDRL and TIMR0..TIMR3. The timer can be started any time by setting bit 'STI' in register CMDRL. After the timer has expired it generates a timer interrupt. The timer can be stopped any time by setting bit 'TRES' in register CMDRL to '1'. The timer is used by the SEROCCO-M for protocol specific time-out and retry transactions in HDLC Automode. (all modes) TMD='1' CNT(2:0) Counter The meaning of this bit field depends on the selected protocol mode. In HDLC Automode, with bit TMD='1': * Retry Counter (in HDLC protocol known as 'N2'): Bit field 'CNT' indicates the number of S-Command frames (with poll bit set) which are transmitted autonomously by SEROCCO-M after every expiration of the time out period 't' (determined by 'TVALUE'), in case an I-Frame gets not acknowledged by the opposite station. The maximum value is 6 S-command frames. If 'CNT' is set to '7', the number of S-commands is unlimited in case of no acknowledgement. In all other modes, with bit TMD='0': * Restart Counter : Bit field 'CNT' indicates the number of automatic restarts which are performed by SEROCCO-M after every expiration of the time-out period 't', in case the timer is not stopped by setting bit 'TRES' in register CMDRL to '1'. The maximum value is 6 restarts. If 'CNT' is set to '7', a timer interrupt is generated periodically with time period 't' determined by bit field 'TVALUE'. Data Sheet 5-199 2000-09-14 PEB 20532 PEF 20532 Register Description (TIMR3) TVALUE (23:0) Timer Expiration Value This bit field determines the timer expiration period 't': (all modes) t = ( TVALUE + 1 ) x CP ('CP' is the clock period, depending on bit 'SRC'.) Data Sheet 5-200 2000-09-14 PEB 20532 PEF 20532 Register Description (XAD1) Register 61 CPU Accessibility: Reset Value: Offset Address: typical usage: XAD1 Transmit Address 1 Register read/write 00H Channel A 3EH Channel B 8EH written by CPU; read and evaluated by SEROCCO-M Bit Mode 7 6 5 4 3 2 1 0 Transmit Address (high) XAD1 (high byte) or XAD1 (COMMAND) 0 XAD1_0 H A B 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Register 62 CPU Accessibility: Reset Value: Offset Address: typical usage: XAD2 Transmit Address 2 Register read/write 00H Channel A 3FH Channel B 8FH written by CPU; read and evaluated by SEROCCO-M Bit Mode 7 6 5 4 3 2 1 0 Transmit Address (low) XAD2 (low byte) or XAD2 (RESPONSE) H A B Data Sheet 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 5-201 2000-09-14 PEB 20532 PEF 20532 Register Description (XAD2) XAD1 and XAD2 bit fields are valid in HDLC modes with automatic address field handling only (Automode, Address Mode 1, Address Mode 2). They can be programmed with one individual address byte which is inserted automatically into the address field (8 or 16 bit) of a HDLC transmit frame. The function depends on the selected protocol mode and address field size (bit 'ADM' in register CCR2L). XAD1 Transmit Address 1 (hdlc modes) - 2-byte address field: Bit field XAD1 constitutes the high byte of the 2-byte address field. Bit 1 must be set to '0'. According to the ISDN LAP-D protocol, bit 1 is interpreted as the C/R (COMMAND/RESPONSE) bit. This bit is manipulated automatically by SEROCCO-M according to the setting of bit 'CRI' in register RAH1. The following is the C/R value (on bit 1), when: - transmitting COMMANDs: '1' (if 'CRI'='1') ; '0' (if 'CRI'='0') - transmitting RESPONSEs: '0' (if 'CRI'='1') ; '1' (if 'CRI'='0') (In ISDN LAP-D, the high byte is known as 'SAPI'.) In accordance with the HDLC protocol, bit 'XAD1_0' should be set to '0', to indicate that the address field contains (at least) one more byte. - 1-byte address field: According to the X.25 LAP-B protocol, XAD1 is the address of a 'COMMAND' frame. XAD2 Transmit Address 2 (hdlc modes) - 2-byte address field: Bit field XAD2 constitutes the low byte of the 2-byte address field. (In ISDN LAP-D, the low byte is known as 'TEI'.) - 1-byte address field: According to the X.25 LAP-B protocol, XAD2 is the address of a 'RESPONSE' frame. Data Sheet 5-202 2000-09-14 PEB 20532 PEF 20532 Register Description (RAL1) Register 63 CPU Accessibility: Reset Value: Offset Address: typical usage: RAL1 Receive Address 1 Low Register read/write 00H Channel A 40H Channel B 90H written by CPU; read and evaluated by SEROCCO-M Bit Mode 7 6 5 4 3 2 1 0 Receive Address 1 (low) RAL1 RAL1 H A B 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Register 64 CPU Accessibility: Reset Value: Offset Address: typical usage: RAH1 Receive Address 1 High Register read/write 00H Channel A 41H Channel B 91H written by CPU; read and evaluated by SEROCCO-M Bit Mode 7 6 5 4 3 2 1 0 Receive Address 1 (high) RAH1 or RAH1 CRI RAH1_0 H A B Data Sheet 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 5-203 2000-09-14 PEB 20532 PEF 20532 Register Description (RAL2) Register 65 CPU Accessibility: Reset Value: Offset Address: typical usage: RAL2 Receive Address 2 Low Register read/write 00H Channel A 42H Channel B 92H written by CPU; read and evaluated by SEROCCO-M Bit Mode 7 6 5 4 3 2 1 0 Receive Address 2 (low) RAL2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 H A B Register 66 CPU Accessibility: Reset Value: Offset Address: typical usage: RAH2 Receive Address 2 High Register read/write 00H Channel A 43H Channel B 93H written by CPU; read and evaluated by SEROCCO-M Bit Mode 7 6 5 4 3 2 1 0 Receive Address 2 (high) RAH2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 H A B Data Sheet 5-204 2000-09-14 PEB 20532 PEF 20532 Register Description (RAH2) In operating modes that provide address recognition, the high/low byte of the received address is compared with the individually programmable values in register RAH2/ RAL2/RAH1/RAL1. This addresses can be masked on a per bit basis by setting the corresponding bits in registers AMRAL1/AMRAH1/AMRAL2/AMRAH2 to allow extended broadcast address recognition. This feature is applicable to all HDLC sub-modes with address recognition. RAH1 Receive Address 1 Byte High (hdlc modes) In HDLC Automode bit '1' is reserved for 'CRI' (Command Response Interpretation). In all other modes RAH1 is an 8 bit address. CRI Command/Response Interpretation The setting of this bit effects the meaning of the 'C/R' bit in the receive status byte (RSTA). This status bit 'C/R' should be interpreted after reception as follows: '0' (if 'CRI'='1') ; '1' (if 'CRI'='0') : COMMAND received '1' (if 'CRI'='1') ; '0' (if 'CRI'='0') : RESPONSE received Note: If 1-byte address field is selected in HDLC Automode, RAH1 must be set to 0x00H. RAL1 Receive Address 1 Byte Low (hdlc modes) The general function and its meaning depends on the selected HDLC operating mode: * Automode / Address Mode 2 (16-bit address) RAL1 can be programmed with the value of the first individual low address byte. * Automode / Address Mode 2 (8-bit address) According to X.25 LAP-B protocol, the address in RAL1 is considered as the address of a 'COMMAND' frame. RAH2 RAL2 Receive Address 2 Byte High Receive Address 2 Byte Low (hdlc modes) (hdlc modes) Value of the second individually programmable high/low address byte. If a 1-byte address field is selected, RAL2 is considered as the address of a 'RESPONSE' frame according to X.25 LAP-B protocol. Data Sheet 5-205 2000-09-14 PEB 20532 PEF 20532 Register Description (AMRAL1) Register 67 CPU Accessibility: Reset Value: Offset Address: typical usage: AMRAL1 Mask Receive Address 1 Low Register read/write 00H Channel A 44H Channel B 94H written by CPU; read and evaluated by SEROCCO-M Bit Mode 7 6 5 4 3 2 1 0 Receive Mask Address 1 (low) AMRAL1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 H A B Register 68 CPU Accessibility: Reset Value: Offset Address: typical usage: AMRAH1 Mask Receive Address 1 High Register read/write 00H Channel A 45H Channel B 95H written by CPU; read and evaluated by SEROCCO-M Bit Mode 7 6 5 4 3 2 1 0 Receive Mask Address 1 (high) AMRAH1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 H A B Data Sheet 5-206 2000-09-14 PEB 20532 PEF 20532 Register Description (AMRAL2) Register 69 CPU Accessibility: Reset Value: Offset Address: typical usage: AMRAL2 Mask Receive Address 2 Low Register read/write 00H Channel A 46H Channel B 96H written by CPU; read and evaluated by SEROCCO-M Bit Mode 7 6 5 4 3 2 1 0 Receive Mask Address 2 (low) AMRAL2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 H A B Register 70 CPU Accessibility: Reset Value: Offset Address: typical usage: AMRAH2 Mask Receive Address 2 High Register read/write 00H Channel A 47H Channel B 97H written by CPU; read and evaluated by SEROCCO-M Bit Mode 7 6 5 4 3 2 1 0 Receive Mask Address 2 (high) AMRAH2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 H A B Data Sheet 5-207 2000-09-14 PEB 20532 PEF 20532 Register Description (AMRAH2) AMRAH2 AMRAL2 AMRAH1 AMRAL1 Receive Mask Address 2 Byte High Receive Mask Address 2 Byte Low Receive Mask Address 1 Byte High Receive Mask Address 1 Byte Low (hdlc modes) (hdlc modes) (hdlc modes) (hdlc modes) Setting a bit in this registers to '1' masks the corresponding bit in registers RAH2/RAL2/RAH1/RAL1. A masked bit position always matches when comparing the received frame address with registers RAH2/RAL2/RAH1/RAL1, allowing extended broadcast mechanism. bit = '0' The dedicated bit position is NOT masked. This bit position in the received address must match with the corresponding bit position in registers RAH2/RAL2/RAH1/ RAL1 to accept the frame. The dedicated bit position is masked. This bit position in the received address NEED NOT match with the corresponding bit position in registers RAH2/RAL2/RAH1/ RAL1 to accept the frame. bit = '1' Data Sheet 5-208 2000-09-14 PEB 20532 PEF 20532 Register Description (RLCRL) Register 71 CPU Accessibility: Reset Value: Offset Address: typical usage: RLCRL Receive Length Check Register (Low Byte) read/write 00H Channel A 48H Channel B 98H written by CPU; read and evaluated by SEROCCO-M Bit Mode 7 6 5 4 3 2 1 0 Receive Length Limit H A B 0 0 0 0 0 0 0 0 RL(7:0) 0 0 0 0 0 0 0 0 Register 72 CPU Accessibility: Reset Value: Offset Address: typical usage: RLCRH Receive Length Check Register (High Byte) read/write 00H Channel A 49H Channel B 99H written by CPU; read and evaluated by SEROCCO-M Bit Mode 7 6 5 4 3 2 1 0 Receive Length Check Control RCE 0 0 Receive Length Limit H A B 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RL(10:8) 0 0 0 0 Data Sheet 5-209 2000-09-14 PEB 20532 PEF 20532 Register Description (RLCRH) RCE Receive Length Check Enable (hdlc modes) This bit is valid in HDLC mode only and enables/disables the receive length check function: RCE = '0' RCE = '1' No receive length check on received HDLC frames is performed. The receive length check is enabled. All bytes of a HDLC frame which are transferred to the receive FIFO (depending on the selected protocol sub-mode and receive CRC handling) are counted and checked against the maximum length check limit which is programmed in bit field 'RL'. A frame exceeding the maximum length is treated as if it were aborted on the receive line ('RME' interrupt and bit 'RAB' (receive abort) set in the RSTA byte). In addition a 'FLEX' interrupt is generated prior to 'RME', if enabled. Note: The Receive Status Byte (RSTA) is part of the frame length checking. RL(10:0) Receive Length Check Limit (hdlc modes) This bit-field defines the receive length check limit (32..65536 bytes) if checking is enabled via bit 'RCE': RL(10:0) The receive length limit is calculated by: Limit = ( RL + 1 ) x 32 Data Sheet 5-210 2000-09-14 PEB 20532 PEF 20532 Register Description (XON) Register 73 CPU Accessibility: Reset Value: Offset Address: typical usage: XON XON In-Band Flow Control Character Register read/write 00H Channel A 4AH Channel B 9AH written by CPU; read and evaluated by SEROCCO-M Bit Mode 7 6 5 4 3 2 1 0 XON Character H A B 0 0 0 0 XON(7:0) 0 0 0 0 0 0 0 0 0 0 0 0 Register 74 CPU Accessibility: Reset Value: Offset Address: typical usage: XOFF XOFF In-Band Flow Control Character Register read/write 00H Channel A 4BH Channel B 9BH written by CPU; read and evaluated by SEROCCO-M Bit Mode 7 6 5 4 3 2 1 0 XOFF Character H A B 0 0 0 0 0 0 0 0 XOFF(7:0) 0 0 0 0 0 0 0 0 Data Sheet 5-211 2000-09-14 PEB 20532 PEF 20532 Register Description (XOFF) XON(7:0) XON Character (async mode) This bit field specifies the XON character for in-band flow control in ASYNC protocol mode. The number of significant bits starting with the LSB depends on the character length (5..8 bits) selected via bit field 'CHL(1:0)' in register CCR3L. A received character is recognized as a valid XON-character, if * the character was correctly framed (character length as programmed and correct parity if checking is enabled) * each bit position of the received character which is not masked via register MXON matches with the corresponding bit in register XON. Received characters recognized as XON character are stored in the receive FIFO as normal receive data unless disabled with bit CCR3L:DXS. An appropriate 'XON' interrupt is generated (if enabled) and the transmitter is switched into 'XON' state if in-band flow control is enabled via bit 'FLON' in register CCR2H. XOFF(7:0) XOFF Character (async mode) This bit field specifies the XOFF character for in-band flow control in ASYNC protocol mode. The number of significant bits starting with the LSB depends on the character length (5..8 bits) selected via bit field 'CHL(1:0)' in register CCR3L. A received character is recognized as a valid XOFF-character, if * the character was correctly framed (character length as programmed and correct parity if checking is enabled) * each bit position of the received character which is not masked via register MXOFF matches with the corresponding bit in register XOFF. Received characters recognized as XOFF character are stored in the receive FIFO as normal receive data unless disabled with bit CCR3L:DXS. An appropriate 'XOFF' interrupt is generated (if enabled) and the transmitter is switched into 'XOFF' state if in-band flow control is enabled via bit 'FLON' in register CCR2H. Data Sheet 5-212 2000-09-14 PEB 20532 PEF 20532 Register Description (MXON) Register 75 CPU Accessibility: Reset Value: Offset Address: typical usage: MXON XON In-Band Flow Control Mask Register read/write 00H Channel A 4CH Channel B 9CH written by CPU; read and evaluated by SEROCCO-M Bit Mode 7 6 5 4 3 2 1 0 XON Character Mask H A B 0 0 0 0 0 0 0 0 MXON(7:0) 0 0 0 0 0 0 0 0 Register 76 CPU Accessibility: Reset Value: Offset Address: typical usage: MXOFF XOFF In-Band Flow Control Mask Register read/write 00H Channel A 4DH Channel B 9DH written by CPU; read and evaluated by SEROCCO-M Bit Mode 7 6 5 4 3 2 1 0 XOFF Character Mask H A B 0 0 0 0 0 0 0 0 MXOFF(7:0) 0 0 0 0 0 0 0 0 Data Sheet 5-213 2000-09-14 PEB 20532 PEF 20532 Register Description (MXOFF) MXON(7:0) XON Character Mask (async mode) Setting a bit in this bit field to '1' masks the corresponding bit in bit field 'XON(7:0)' of register XON. A masked bit position always matches when comparing the received character with bit field 'XON(7:0)'. bit = '0' The dedicated bit position is NOT masked. This bit position in the received character must match with the corresponding bit position in bit field 'XON' to recognize the received character as an XON character. The dedicated bit position is masked. This bit position in the received character NEED NOT match with the corresponding bit position in bit field 'XON' to recognize the received character as an XON character. (async mode) bit = '1' MXOFF(7:0) XOFF Character Mask Setting a bit in this bit field to '1' masks the corresponding bit in bit field 'XOFF(7:0)' of register XOFF. A masked bit position always matches when comparing the received character with bit field 'XOFF(7:0)'. bit = '0' The dedicated bit position is NOT masked. This bit position in the received character must match with the corresponding bit position in bit field 'XOFF' to recognize the received character as an XOFF character. The dedicated bit position is masked. This bit position in the received character NEED NOT match with the corresponding bit position in bit field 'XOFF' to recognize the received character as an XOFF character. bit = '1' Data Sheet 5-214 2000-09-14 PEB 20532 PEF 20532 Register Description (TCR) Register 77 CPU Accessibility: Reset Value: Offset Address: typical usage: TCR Termination Character Register read/write 00H Channel A 4EH8 Channel B 9EH written by CPU; read and evaluated by SEROCCO-M Bit Mode 7 6 5 4 3 2 1 0 Termination Character H A B 0 0 0 0 TC(7:0) TC(7:0) 0 0 0 0 TC(7:0) Termination Character (async mode) This bit-field defines the termination character which is monitored on the receive data stream if enabled via bit 'TCDE' in register CCR3L. Data Sheet 5-215 2000-09-14 PEB 20532 PEF 20532 Register Description (TICR) Register 78 CPU Accessibility: Reset Value: Offset Address: typical usage: TICR Transmit Immediate Character Register read/write 00H Channel A 4FH Channel B 9FH written by CPU; read and evaluated by SEROCCO-M Bit Mode 7 6 5 4 3 2 1 0 Transmit Immediate Character H A B 0 0 0 0 TIC(7:0) 0 0 0 0 0 0 0 0 0 0 0 0 Data Sheet 5-216 2000-09-14 PEB 20532 PEF 20532 Register Description (TICR) TIC Transmit Immediate Character (async mode) On write access to this register, the ASYNC protocol engine will automatically insert the character defined by bit field 'TIC' into the transmit data stream. This happens * immediately after write access to register TICR if the transmitter is in IDLE state (no other character is currently transmitted). The transmitter returns to IDLE state after transmission of the TIC. * immediately after the character which is currently in transmission is completed. After transmission of the TIC, the transmitter continues with transmission of characters which are still stored in the transmit FIFO. Thus the TIC is inserted into the data stream between the characters provided via the transmit FIFO. The TIC transmission is independent of in-band flow control. Thus the TIC is sent out even if the transmitter is in 'XOFF' state. However the transmitter must be enabled via signal CTS (depending on bit 'FCTS' in register CCR1H). The number of significant bits (starting with the LSB) depends on the character length programmed in bit field 'CHL(1:0)' in register CCR3L. All character framing related settings in registers CCR3L/CCR3H (start bit, parity generation, number of stop bits) also apply to the TIC character framing. As long as the TIC character is not completely sent, status bit TIC Execution ('TEC') in status register STARL is set to '1' by SEROCCO-M. No further write access to register TICR is allowed until 'TEC' status indication is cleared by SEROCCO-M. Data Sheet 5-217 2000-09-14 PEB 20532 PEF 20532 Register Description (ISR0) Register 79 CPU Accessibility: Reset Value: Offset Address: typical usage: ISR0 Interrupt Status Register 0 read only 00H Channel A 50H Channel B A0H updated by SEROCCO-M read and evaluated by CPU Bit Mode 7 6 5 4 ISR0 3 2 1 0 H A B RDO 0 0 RFO RFO RFO PCE FERR SCD RSC PERR PERR RPF RPF RPF RME TCD TCD RFS TIME 0 FLEX 0 0 Register 80 CPU Accessibility: Reset Value: Offset Address: typical usage: ISR1 Interrupt Status Register 1 read only 00H Channel A 51H Channel B A1H updated by SEROCCO-M read and evaluated by CPU Bit Mode 7 6 5 4 ISR1 3 2 1 0 H A B TIN TIN TIN CSC CSC CSC XMR XOFF XMR XPR XPR XPR ALLS ALLS ALLS XDU XON XDU SUEX BRK 0 0 BRKT 0 Data Sheet 5-218 2000-09-14 PEB 20532 PEF 20532 Register Description (ISR2) Register 81 CPU Accessibility: Reset Value: Offset Address: typical usage: ISR2 Interrupt Status Register 2 read only 00H Channel A 52H Channel B A2H updated by SEROCCO-M read and evaluated by CPU Bit Mode 7 6 5 4 ISR2 3 2 1 0 H A B 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PLLA PLLA PLLA CDSC CDSC CDSC Data Sheet 5-219 2000-09-14 PEB 20532 PEF 20532 Register Description (ISR2) RDO Receive Data Overflow Interrupt (hdlc mode) This bit is set to '1', if receive data of the current frame got lost because of a SCC receive FIFO full condition. However the rest of the frame is received and discarded as long as the receive FIFO remains full and is stored as soon as FIFO space is available again. The receive status byte (RSTA) of such a frame contains an 'RDO' indication. In DMA operation the 'RDO' indication is also set in the receive byte count register RBCH. RFO Receive FIFO Overflow Interrupt HDLC Mode: This bit is set to '1', if the SCC receive FIFO is full and a complete frame must be discarded. This interrupt can be used for statistical purposes, indicating that the host was not able to service the SCC receive FIFO quickly enough, e.g. due to high bus latency. ASYNC/BISYNC Mode: This bit is set to '1', if the SCC receive FIFO is full and another received character has been discarded. This interrupt can be used for statistical purposes and might indicate that the host was not able to service the SCC receive FIFO quickly enough, e.g. bus latencies are too high. PCE Protocol Error Interrupt This bit is valid in HDLC Automode only. It is set to '1', if the receiver has detected a protocol error, i.e. one of the following events occured: * an S- or I-frame was received with wrong N(R) counter value; * an S-frame containing an Information field was received. FERR Framing Error Interrupt (async mode) (hdlc mode) (all modes) This bit is set to '1', if a character framing error is detected, i.e. a '0' was sampled at a position where a stop bit '1' was expected due to the selected character format. Data Sheet 5-220 2000-09-14 PEB 20532 PEF 20532 Register Description (ISR2) SCD Sync Character Detected (bisync mode) Only valid in Hunt Mode. This bit is set to '1' if a SYN character is found in the received data stream after the 'HUNT' command has been issued in register CMDRH. The receiver now is in the synchronous state. RSC Receive Status Change Interrupt (hdlc mode) This bit is valid in HDLC Automode only. It is set to '1', if a status change of the remote station receiver has been detected by receiving a S-frame with receiver ready (RR) or receiver not ready (RNR) indication. Because only a status change is indicated via this interrupt, the current status can be evaluated by reading bit 'RRNR' in status register STARH. PERR Parity Error Interrupt (async/bisync modes) This bit is only valid if parity checking/generation is enabled via bit 'PARE' in register CCR3H. It is set to '1', if a character with wrong parity has been received. If enabled via bit CCR3H:RFDF, this error status is additionally stored in the receive status byte generated for each receive character. RPF Receive Pool Full Interrupt (all modes) This bit is set to '1' if the RFIFO threshold level, set with bit field 'RFTH(1:0)' in register CCR3H, is reached. Default threshold level is 32 data bytes in HDLC/PPP modes, 1 data byte in ASYNC/BISYNC modes. Data Sheet 5-221 2000-09-14 PEB 20532 PEF 20532 Register Description (ISR2) RME Receive Message End Interrupt (hdlc mode) This bit set to '1' indicates that the reception of one message is completed, i.e. either - one message which fits into RFIFO not exceeding the receive FIFO threshold, or - the last part of a message, all in all exceeding the receive FIFO threshold is stored in the RFIFO. The complete message length can be determined by reading the RBCL/ RBCH registers. The number of bytes stored in RFIFO is given by the 5, 4, 2 or 1 least significant bits of register RBCL, depending on the selected RFIFO threshold (bit field 'RFTH(1:0)' in register CCR3H). Additional frame status information is available in the RSTA byte, stored in the RFIFO as the last byte of each frame. Note: After the RFIFO contents have been read, an CMDRH:RMC command must be issued to free the RFIFO for new receive data. TCD Termination Character Detected Interrupt (async/bisync mode) This bit is set to '1', if a termination character (TCR) has been detected in the receive data stream or an 'RFRD' command, issued in the CMDRH register, has been completed. The SCC will insert a 'block end' indication to the RFIFO. The actual block length can be determined by reading register RBCL. Note: After the RFIFO contents have been read, an CMDRH:RMC command must be issued to free the RFIFO for new receive data. RFS Receive Frame Start Interrupt (hdlc mode) This bit is set to '1', if the beginning of a valid frame is detected by the receiver. A valid frame start is detected either if a valid address field is recognized (in all operating modes with address recognition) or if a start flag is recognized (in all operating modes with no address recognition). TIME Time Out Interrupt (async mode) This bit is set to '1', if the time out limit is exceeded, i.e. no new character was received in a programmable period of time (refer to register TOLEN bit fields 'TOIE' and 'TOLEN' for more information). Data Sheet 5-222 2000-09-14 PEB 20532 PEF 20532 Register Description (ISR2) FLEX Frame Length Exceeded Interrupt (hdlc mode) This bit is set to '1', if the frame length check feature is enabled and the current received frame is aborted because the programmed frame length limit was exceeded (refer to registers RLCRL/RLCRH for detailed description). TIN Timer Interrupt (all modes) This bit is set to '1', if the internal timer was activated and has expired (refer also to description of timer registers TIMR0..TIMR3). CSC CTS Status Change (all modes) This bit is set to '1', if a transition occurs on signal CTS. The current state of signal CTS is monitored by status bit 'CTS' in status register STARL. Note: A transmit clock must be provided to detect a transition of CTS. XMR Transmit Message Repeat (hdlc/bisync modes) This bit is set to '1', if transmission of the last frame has to be repeated (by software), because * the SCC has received a negative acknowledge to an I-frame (in HDLC Automode operation); * a collision occured after at least 14.5 bytes of data have been completely sent out, i.e. automatic re-transmission cannot be performed by the SCC; * CTS signal was deasserted after at least 14.5bytes of data have been completely sent out. Note: For easy recovery from a collision event (in bus configuration only), the SCC transmit FIFO should not contain more than one complete frame. This can be achieved by using the 'ALLS' interrupt to control the corresponding transmit channel forwarding a new frame on all sent (ALLS) event only. XOFF XOFF Character Detected Interrupt ASYNC Mode: This bit is set to '1', if the currently received character matched the XOFF character programmed in register XOFF and indicates, that the transmitter is switched to 'XOFF' state if in-band flow control is enabled via bit 'FLON' in register CCR2H. (async mode) Data Sheet 5-223 2000-09-14 PEB 20532 PEF 20532 Register Description XPR Transmit Pool Ready Interrupt (all modes) This bit is set to '1', if a transmitter reset command was executed successfully (command bit 'XRES' in register CMDRL) and whenever the XFIFO is able to accept new transmit data again. An 'XPR' interrupt is not generated, if no sufficient transmit clock is available (depending on the selected clock mode). ALLS ALL Sent Interrupt HDLC Mode: This bit is set to '1': * if the last bit of the current HDLC frame is sent out via pin TxD and no further frame is stored in the SCC transmit FIFO, i.e. the transmit FIFO is empty (Address Mode 2/1/0); * if an I-frame is sent out completely via pin TxD and either a valid acknowledge S-frame has been received or a time-out condition occured because no valid acknowledge S-frame has been received in time (Automode). ASYNC/BISYNC Mode: This bit is set to '1', if the last character is completely sent via pin TxD and no further data is stored in the SCC transmit FIFO, i.e. the transmit FIFO is empty. XDU Transmit Data Underrun Interrupt (hdlc/bisync modes) (all modes) This bit is set to '1', if the current frame was terminated by the SCC with an abort sequence, because neither a 'frame end / block end' indication was detected in the FIFO (to complete the current frame) nor more data is available in the SCC transmit FIFO. Note: The transmitter is stopped if this condition occurs. The XDU condition MUST be cleared by reading register ISR1, thus bit 'XDU' should not be masked via register IMR1. XON XON Character Detected Interrupt (async mode) This bit is set to '1', if the currently received character matched the XON character programmed in register XON and indicates, that the transmitter is switched to 'XON' state if in-band flow control is enabled via bit 'FLON' in register CCR2H. Data Sheet 224 2000-09-14 PEB 20532 PEF 20532 Register Description SUEX Signalling Unit Counter Exceeded Interrupt (hdlc mode) This bit is set to '1', if 256 correct or incorrect SU's have been received and the internal counter is reset to 0. BRK Break Interrupt (async mode) This bit is set to '1', if a break condition was detected on the receive line, i.e. a low level for a time equal to (character length + parity bit + stop bit(s)) bits depending on the selected ASYNC character format. BRKT Break Terminated Interrupt (async mode) This bit is set to '1', if a previously detected break condition on the receive line is terminated by a low to high transition. PLLA DPLL Asynchronous Interrupt (all modes) This bit is only valid, if the receive clock is derived from the internal DPLL and FM0, FM1 or Manchester data encoding is selected (depending on the selected clock mode and data encoding mode). It is set to '1' if the DPLL has lost synchronization. Reception is disabled until synchronization has been regained again. If the transmitter is supplied with a clock derived from the DPLL, transmission is also interrupted. CDSC Carrier Detect Status Change Interrupt (all modes) This bit is set to '1', if a state transition has been detected at signal CD. Because only a state transition is indicated via this interrupt, the current status can be evaluated by reading bit 'CD' in status register STARH. Note: A receive clock must be provided to detect a transition of CD. Data Sheet 225 2000-09-14 PEB 20532 PEF 20532 Register Description Register 82 CPU Accessibility: Reset Value: Offset Address: typical usage: IMR0 Interrupt Mask Register 0 read/write FFH Channel A 54H Channel B A4H written by CPU; read and evaluated by SEROCCO-M Bit Mode 7 6 5 4 IMR0 3 2 1 0 H A B RDO 1 1 RFO RFO RFO PCE FERR SCD RSC PERR PERR RPF RPF RPF RME TCD TCD RFS TIME 1 FLEX 1 1 Register 83 CPU Accessibility: Reset Value: Offset Address: typical usage: IMR1 Interrupt Mask Register 1 read/write FFH Channel A 55H Channel B A5H written by CPU; read and evaluated by SEROCCO-M Bit Mode 7 6 5 4 IMR1 3 2 1 0 H A B TIN TIN TIN CSC CSC CSC XMR XOFF XMR XPR XPR XPR ALLS ALLS ALLS XDU XON XDU SUEX BRK 1 1 BRKT 1 Data Sheet 226 2000-09-14 PEB 20532 PEF 20532 Register Description Register 84 CPU Accessibility: Reset Value: Offset Address: typical usage: IMR2 Interrupt Mask Register 2 read/write 03H Channel A 56H Channel B A6H written by CPU; read and evaluated by SEROCCO-M Bit Mode 7 6 5 4 IMR2 3 2 1 0 H A B 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PLLA PLLA PLLA CDSC CDSC CDSC Data Sheet 227 2000-09-14 PEB 20532 PEF 20532 Register Description (IM) Interrupt Mask Bits Each SCC interrupt event can generate an interrupt signal indication via pin INT/INT. Each bit position of registers IMR0..IMR2 is a mask for the corresponding interrupt event in the interrupt status registers ISR0..ISR2. Masked interrupt events never generate an interrupt indication via pin INT/INT. bit = '0' bit = '1' The corresponding interrupt event is NOT masked and will generate an interrupt indication via pin INT/INT. The corresponding interrupt event is masked and will NEITHER generate an interrupt vector NOR an interrupt indication via pin INT/INT. Moreover, masked interrupt events are: * not displayed in the interrupt status registers ISR0..ISR2 if bit 'VIS' in register CCR0L is programmed to '0'. * displayed in interrupt status registers ISR0..ISR2 if bit 'VIS' in register CCR0L is programmed to '1'. Note: After RESET, all interrupt events are masked. Undefined bits must not be cleared to '0'. For detailed interrupt event description refer to the corresponding bit position in registers ISR0..ISR2. Data Sheet 228 2000-09-14 PEB 20532 PEF 20532 Register Description Register 85 CPU Accessibility: Reset Value: Offset Address: typical usage: RSTA Receive Status Byte read only 00H Channel A 58H Channel B A8H written by SEROCCO-M to RFIFO; read from RFIFO and evaluated by CPU Bit Mode 7 6 5 4 3 2 1 0 Receive Status Byte VFR RDO CRCOK RAB HA(1:0)/ SU(1:0) 0 0 0 0 C/R LA H A B PE PE FE 0 0 0 0 0 0 0 P P The Receive Status Byte 'RSTA' contains comprehensive status information about the last received frame (HDLC/PPP) or the last received ASYNC/BISYNC character. The SCC attaches this status byte to the receive data and thus it should be read from the RFIFO. In HDLC/PPP modes the RSTA value can optionally be read from this register address; in ASYNC and BISYNC modes a read to this register is not specified. In extended transparent mode this status field does not apply. Data Sheet 229 2000-09-14 PEB 20532 PEF 20532 Register Description VFR Valid Frame Determines whether a valid frame has been received. VFR='0' (hdlc modes) The received frame is invalid. An invalid frame is either a frame which is not an integer number of 8 bits (n * 8 bits) in length (e.g. 25 bits), or a frame which is too short, taking into account the operation mode selected via CCR2L (MDS1, MDS0, ADM) and the selected CRC algorithm (CCR1L:C32) as follows: for CCR3H:DRCRC = '0' (CRC reception enabled): * automode / address mode 2 (16-bit address) 4 bytes (CRC-CCITT) or 6 (CRC-32) * automode / address mode 2 (8-bit address) 3 bytes (CRC-CCITT) or 5 (CRC-32) * address mode 1: 3 bytes (CRC-CCITT) or 5 (CRC-32) * address mode 0: 2 bytes (CRC-CCITT) or 4 (CRC-32) for CCR3H:DRCRC = '1' (CRC reception disabled): * automode / address mode 2 (16-bit address): 2 bytes * automode / address mode 2 (8-bit address): 1 byte * address mode 1: 1 byte * address mode 0: 1 byte Note: Shorter frames are not reported at all. VFR='1' RDO The received frame is valid. (hdlc modes) Receive Data Overflow RDO='0' RDO='1' No receive data overflow has occurred. A data overflow has occurred during reception of the frame. Additionally, an interrupt can be generated (refer to ISR0:RDO/IMR0:RDO). Data Sheet 230 2000-09-14 PEB 20532 PEF 20532 Register Description CRCOK CRC Compare/Check CRCOK='0' CRCOK='1' (hdlc modes) CRC check failed, received frame contains errors. CRC check OK; the received frame does not contain CRC errors. (hdlc modes) RAB Receive Message Aborted RAB='0' RAB='1' No abort condition was detected during reception of the frame. The received frame was aborted from the transmitting station. According to the HDLC protocol, this frame must be discarded by the receiver station. This bit is also set to '1' if the maximum receive byte count (set in registers RLCRL/RLCRH) is reached. (hdlc modes) HA(1:0) High Byte Address Compare Significant only if an address mode with automatic address handling has been selected. In operating modes which provide high byte address recognition, SEROCCO-M compares the high byte of a 2-byte address with the contents of two individually programmable addresses (RAH1, RAH2) and the fixed values FEH and FCH (broadcast address). Dependent on the result of this comparison, the following bit combinations are possible: HA(1:0)='10' RAH1 has been recognized. HA(1:0)='00' RAH2 has been recognized. HA(1:0)='01' broadcast address has been recognized. If RAH1 and RAH2 contain identical values, a match is indicated by HA(1:0)='10'. SU(1:0) SS7 Signaling Unit Type (hdlc modes) If Signaling System #7 support is activated (see CCR3L register, bit 'ESS7'), the bit functions are defined as follows: SU(1:0)='00' not valid SU(1:0)='01' Fill In Signaling Unit (FISU) detected SU(1:0)='10' Link Status Signaling Unit (LSSU) detected SU(1:0)='11' Message Signaling Unit (MSU) detected Data Sheet 231 2000-09-14 PEB 20532 PEF 20532 Register Description C/R Command/Response (hdlc modes) Significant only if 2-byte address mode has been selected. Value of the C/R bit (bit 1 of high address byte) in the received frame. The interpretation depends on the setting of the 'CRI' bit in the RAH1 register (See "RAH1" on page 203.). LA Low Byte Address Compare (hdlc modes) Significant in automode and address mode 2 only. The low byte address of a 2-byte address field, or the single address byte of a 1-byte address field is compared with two addresses (RAL1, RAL2). LA='0' LA='1' RAL2 has been recognized. RAL1 has been recognized. According to the X.25 LAPB protocol, RAL1 is interpreted as the address of a COMMAND frame and RAL2 is interpreted as the address of a RESPONSE frame. P '1' FE '1' Parity (async/bisync mode) This bit carries the parity bit of the last received character. Framing Error (async mode) A character framing error was detected, i.e. a '0' was sampled at a bit position where a stop bit '1' was expected due to the selected character format. Parity Error (async/bisync mode) PE '1' The calculated parity did not match the received parity bit. Optionally the interrupt PERR can be generated. Data Sheet 232 2000-09-14 PEB 20532 PEF 20532 Register Description Register 86 CPU Accessibility: Reset Value: Offset Address: typical usage: SYNCL SYN Character Register (Low Byte) read/write 00H Channel A 5AH Channel B AAH written by CPU; read and evaluated by SEROCCO-M Bit Mode 7 6 5 4 3 2 1 0 SYN Character Low H A B 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SYNCL(7:0) Register 87 CPU Accessibility: Reset Value: Offset Address: typical usage: SYNCH SYN Character Register (High Byte) read/write 00H Channel A 5BH Channel B ABH written by CPU; read and evaluated by SEROCCO-M Bit Mode 7 6 5 4 3 2 1 0 SYN Character High H A B 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SYNCH(7:0) Data Sheet 233 2000-09-14 PEB 20532 PEF 20532 Register Description SYNCH(7:0) Synchronization Character (high) SYNCL(7:0) Synchronization Character (low) (bisync mode) (bisync mode) This register is only valid in BISYNC protocol mode. The synchronization (SYN) character format depends on the setting of bit 'BISNC' and 'SLEN' in register CCR2L: * MONOSYNC Mode (CCR2L.BISNC = '0') The SYN character is defined by register 'SYNCL': a) SLEN = '0': the 6 bit SYN character is specified by bits (5..0) b) SLEN = '1': the 8 bit SYN character is specified by bits (7..0). * BISYNC Mode (CCR2L.BISNC = '1') The SYN character is defined by registers 'SYNCL' and 'SYNCH': a) SLEN = '0': the 12 bit SYN character is specified by bits (5..0) of each register, i.e. SYN(11..0) = SYNCH(5:0), SYNCL(5:0) b) SLEN = '1': the 16 bit SYN character is specified by bits (7..0) of each register, i.e. SYN(15..0) = SYNCH(7:0), SYNCL(7:0). In transmit direction the SYN character is sent continuously if no data has to be transmitted and interframe timefill control is enabled by setting bit 'ITF' to '1' in register CCR2H. In receive direction the receiver monitors the data stream for occurence of the specified SYN pattern if operating in 'HUNT' mode (bit 'HUNT' in register CMDRH). Data Sheet 234 2000-09-14 PEB 20532 PEF 20532 Register Description 5.2.3 Channel Specific DMA Registers Each register description is organized in three parts: * a head with general information about reset value, access type (read/write), channel specific offset address and usual handling; * a table containing the bit information (name of bit positions); * a section containing the detailed description of each bit. Data Sheet 235 2000-09-14 PEB 20532 PEF 20532 Register Description Register 88 XBCL Transmit Byte Count (Low Byte) CPU Accessibility: Reset Value: Offset Address: typical usage: read/write 00H Channel A B8H Channel B D2H written by CPU, evaluated by SEROCCO-M Bit 7 6 5 4 3 2 1 0 XBC(7:0) Register 89 XBCH Transmit Byte Count (High Byte) CPU Accessibility: Reset Value: Offset Address: typical usage: read/write 00H Channel A B9H Channel B D3H written by CPU, evaluated by SEROCCO-M Bit 7 6 5 4 3 2 1 0 XME XF XIF 0 XBC(11:8) Data Sheet 236 2000-09-14 PEB 20532 PEF 20532 Register Description XBC (11:0) Transmit Byte Count This register is used in DMA Mode only, to program the length (1...4096 bytes) of the next frame to be transmitted. The length of the block in number of bytes is: Length = XBC + 1 This allows the SEROCCO-M to request the correct amount of DMA cycles after an 'XF' or' XIF' command. XME Transmit Message End Command Only valid in external DMA controller mode. This bit is identical to 'XME' command bit (refer to register "CMDRL" on Page 146). XF Transmit Frame Command Only valid in external DMA controller mode. This bit is identical to 'XF' command bit (refer to register "CMDRL" on Page 146). XIF Transmit I-Frame Command Only valid in external DMA controller mode. This bit is identical to 'XIF' command bit (refer to register "CMDRL" on Page 146). Data Sheet 237 2000-09-14 PEB 20532 PEF 20532 Register Description Register 90 RMBSL Receive Maximum Buffer Size (Low Byte) CPU Accessibility: Reset Value: Offset Address: typical usage: Bit 7 read/write 00H Channel A C4H Channel B DEH written by CPU, evaluated by SEROCCO-M 6 5 4 3 2 1 0 Receive Maximum Buffer Size RMBS(7:0) Register 91 RMBSH Receive Maximum Buffer Size (High Byte) CPU Accessibility: Reset Value: Offset Address: typical usage: Bit 15 read/write 00H Channel A C5H Channel B DFH written by CPU, evaluated by SEROCCO-M 14 13 12 11 10 9 8 Receive Maximum Buffer Size RE DRMBS 0 0 RMBS(11:8) Data Sheet 238 2000-09-14 PEB 20532 PEF 20532 Register Description RE Receive DMA Enable Only valid if external DMA controller support is enabled. Self-clearing command bit: RE='0' RE='1' The DMA controller is not set up to forward receive data into a buffer in memory. Setting this bit to '1' enables the DMA support logic to request the external DMA controller to transfer receive data when available in RFIFO. DRMBS Disable Receive Maximum Buffer Size (RMBS) Check Only valid if external DMA controller support is enabled. DRMBS='0' DRMBS='1' Evaluation of bit field RMBS(11:0) is enabled. Evaluation of bit field RMBS(11:0) is disabled. RMBS(11:0) Receive Maximum Buffer Size Only valid if external DMA controller support is enabled. The size of the receive buffer in host memory can be set up in this bit field to ensure that request for DMA transfers are inhibited when the maximum buffer size is reached. An RBF interrupt is generated (if unmasked) to inform the CPU. If the external DMA controller supports this function, it can be disabled by setting bit 'DRMBS' to '1'. Data Sheet 239 2000-09-14 PEB 20532 PEF 20532 Register Description Register 92 RBCL Receive Byte Count (Low Byte) CPU Accessibility: Reset Value: Offset Address: typical usage: read only 00H Channel A C6H Channel B E0H written by SEROCCO-M, evaluated by CPU Bit 7 6 5 4 3 2 1 0 RBC(7:0) Register 93 RBCH Receive Byte Count (High Byte) CPU Accessibility: Reset Value: Offset Address: typical usage: read only 00H Channel A C7H Channel B E1H written by SEROCCO-M, evaluated by CPU Bit 7 6 5 4 3 2 1 0 RBCO 0 0 0 RBC(11:8) Data Sheet 240 2000-09-14 PEB 20532 PEF 20532 Register Description RBC(11:0) Receive Byte Count This bit field determines the receive byte count (1..4095) of the currently received frame/block. RBCO Receive Byte Counter Overflow Only valid in DMA controller mode. This bit indicates an overflow of the receive byte conter RBC(11:0), i.e. the receive frame length exceeded 4095 bytes. Data Sheet 241 2000-09-14 PEB 20532 PEF 20532 Register Description 5.2.4 Miscellaneous Registers VER0 Version Register 0 Register 94 CPU Accessibility: Reset Value: Offset Address: typical usage: read only 83H ECH evaluated by CPU Bit 7 6 5 4 Manufacturer Code 3 2 1 0 Fix '1' VER(7:0) Register 95 VER1 Version Register 1 CPU Accessibility: Reset Value: Offset Address: typical usage: read only E0H EDH evaluated by CPU Bit 7 6 5 4 3 2 1 0 Device Code (bits 3 .. 0) Manufacturer Code VER(15:8) Data Sheet 242 2000-09-14 PEB 20532 PEF 20532 Register Description Register 96 VER2 Version Register 2 CPU Accessibility: Reset Value: Offset Address: typical usage: read only 05H EEH evaluated by CPU Bit 7 6 5 4 3 2 1 0 Device Code (bits 11 .. 4) VER(23:16) Register 97 VER3 Version Register 3 CPU Accessibility: Reset Value: Offset Address: typical usage: read only 20H EFH evaluated by CPU Bit 7 6 5 4 3 2 1 0 Version Number Device Code (bits 15 .. 12) VER(31:24) Data Sheet 243 2000-09-14 PEB 20532 PEF 20532 Register Description VER(31:0) Version Register Identical to 32 bit boundary scan ID string. The 32 bit string consists of the bit fields: VER(31:28) VER(27:12) VER(11:0) 2H 005EH 083H Version Number Device Code Manufacturer Code (LSB fixed to '1') Data Sheet 244 2000-09-14 PEB 20532 PEF 20532 Programming 6 6.1 Programming Initialization After Reset the CPU has to write a minimum set of registers and an optional set depending on the required features and operating modes. First, the following initialization steps must be taken: * Select serial protocol mode (refer to Table 12 "Protocol Mode Overview" on Page 82), * Select encoding of the serial data (refer to Chapter 3.2.13 "Data Encoding" on Page 73), * Program the output characteristics of - pin TxD (selected with bit 'ODS' in "Channel Configuration Register 1 (Low Byte)" on Page 155) and - interrupt pin INT/INT (selected with bit field 'IPC(1:0)' in "Global Mode Register" on Page 122), * Choose a clock mode (refer to Table 7 "Overview of Clock Modes" on Page 46). * Power-up the oscillator unit (with or without shaper) by re-setting bit GMODE:OSCPD to '0', if appropriate (GMODE:DSHP='0' enables the shaper). The clock mode must be set before power-up (CCR0H.PU). The CPU may switch the SEROCCO-M between power-up and power-down mode. This has no influence upon the contents of the registers, i.e. the internal state remains stored. In power-down mode however, all internal clocks are disabled, no interrupts from the corresponding channel are forwarded to the CPU. This state can be used as a standby mode, when the channel is (temporarily) not used, thus substantially reducing power consumption. The SEROCCO-M should usually be initialized in Power-Down mode. The need for programming further registers depends on the selected features (serial mode, clock mode specific features, operating mode, address mode, user demands). 6.2 6.2.1 Interrupt Mode Data Transmission (Interrupt Driven) In transmit direction 2 32 byte FIFO buffers (transmit pools) are provided for each channel. After checking the XFIFO status by polling the Transmit FIFO Write Enable bit (bit 'XFW' in STARL register) or after a Transmit Pool Ready ('XPR') interrupt, up to 32 bytes may be entered by the CPU into the XFIFO. Data Sheet 245 2000-09-14 PEB 20532 PEF 20532 Programming HDLC/SDLC/PPP The transmission of a packet can be started by issuing an 'XF' or 'XIF' command via the CMDRL register. If enabled, a specified number of preambles (refer to registers CCR2H and PREAMB) are sent out optionally before transmission of the current packet starts. If the transmit command does not include an end of message indication (CMDRL.XME), SEROCCO-M will repeatedly request for the next data block by means of an 'XPR' interrupt as soon as no more than 32 bytes are stored in the XFIFO, i.e. a 32-byte pool is accessible to the CPU. This process will be repeated until the CPU indicates the end of message per 'XME' command, after which packet transmission is finished correctly by appending the CRC and closing flag sequence. Consecutive packets may be transmitted as back-to-back packets and may even share a flag (enabled via CCR1L.SFLG), if service of XFIFO is quick enough. In case no more data is available in the XFIFO prior to the arrival of the end-of-message indiction ('XME'), the transmission of the packet is terminated with an abort sequence and the CPU is notified per interrupt (ISR1.XDU, transmit data underrun). The packet may also be aborted per software at any time (CMDRL.XRES). The data transmission sequence, from the CPU's point of view, is outlined in Figure 56. ASYNC The transmission of character(s) can be started by issuing a 'XF' command via the CMDRL register. SEROCCO-M will repeatedly request for the next data block by means of an 'XPR' interrupt as soon as no more than 32 bytes are stored in the XFIFO, i.e. a 32-byte pool is accessible to the CPU. Transmission may be aborted per software (CMDRL.XRES). BISYNC The transmission of a block can be started by issuing an 'XF' command via the CMDRL register. Further handling of data transmission with respect to preamble transmission and command 'XME' is similar to HDLC/SDLC mode. After 'XME' command has been issued, the block is finished by appending the internally generated CRC if enabled (refer to description of register CCR2H). In case no more data is available in the XFIFO prior to the arrival of 'XME', the transmission of the block is terminated with IDLE and the CPU is notified per interrupt (ISR1.XDU). The block may also be aborted per software (CMDRL.XRES). The data transmission flow, from the CPU's point of view, is outlined in Figure 56. Data Sheet 246 2000-09-14 PEB 20532 PEF 20532 Programming START Action taken by CPU Interrupt indication to CPU Reset Transmitter (CMDRL.XRES) Action taken by the SCC 'XPR' Interrupt Transmit serial data XFIFO READY Transmit serial data and append trailer Issue Command CMDRL.XF or CMDRL.XIF Write Data to XFIFO (up to 32 bytes) Issue Command CMDRL.XF+.XME or CMDRL.XIF+.XME No End of Message ? Yes Figure 56 Interrupt Driven Data Transmission (Flow Diagram) 6.2.2 Data Reception (Interrupt Driven) Also 2 32 byte FIFO buffers (receive pools) are provided for each channel in receive direction. There are different interrupt indications concerned with the reception of data: HDLC/SDLC/PPP 'RPF' (Receive Pool Full) interrupt, indicating that a specified number of bytes (limited with the receive FIFO threshold in register CCR3H, bit field 'RFTH(1..0)'; default is 32 bytes) can be read from RFIFO and the received message is not yet complete. * 'RME' (Receive Message End) interrupt, indicating that the reception of one message is completed, i.e. either - one message which fits into RFIFO not exceeding the receive FIFO threshold, or - the last part of a message, all in all exceeding the receive FIFO threshold is stored in the RFIFO. * In addition to the message end ('RME') interrupt the following information about the received packet is stored by SEROCCO-M in special registers and/or RFIFO: Data Sheet 247 2000-09-14 PEB 20532 PEF 20532 Programming Table 16 Status Information after RME interupt Location registers RBCH, RBCL RSTA register (or last byte of received data) RSTA register (or last byte of received data) RSTA register (or last byte of received data) RSTA register (or last byte of received data) RSTA register (or last byte of received data) Status Information Length of received message CRC result (good/bad) Valid frame (yes/no) ABORT sequence recognized (yes/no) Data overflow (yes/no) Results from address comparison (with automatic address handling) Type of frame (COMMAND/RESPONSE) RSTA register (or last byte of received data) (with automatic address handling) Type of Signaling Unit (in SS7 mode) ASYNC, BISYNC * 'RPF' (Receive Pool Full) interrupt, indicating that a specified number of bytes (refer to register CCR3H, bit field 'RFTH(1..0)') can be read from RFIFO. * 'TCD' (Termination Character Detected) interrupt, indicating that reception has been terminated by reception of a specified character (refer to register TCR and bit CCR3L.TCDE). Additionally, the CPU can have access to contents of RFIFO without having received an interrupt (and thereby causing 'TCD' to occur) by issuing the RFIFO Read command (CMDRH.RFRD). In addition to every received character the assigned status information Parity bit (0/1), Parity Error (yes/no), Framing Error (yes/no, ASYNC only!) is optionally stored in RFIFO. With an end condition ('TCD' interrupt or after 'RFRD' command) the length of the last received data block is stored in register RBCL. The number of bytes to read from RFIFO is determined by the 1, 2, 4 or 5 least significant bits of register RBCL, depending on the selected RFIFO threshold (bit field 'RFTH(1..0)' in register CCR3H). Note: (For all serial modes) After the received data has been read from the RFIFO, this must be explicitly acknowledged by the CPU issuing an 'RMC' (Receive Message Complete) command. The CPU has to handle the 'RPF' interrupt before the complete 2 x 32-byte FIFO is filled up with receive data which would cause a "Receive Data Overflow" condition. The data reception sequence, from the CPU's point of view, is outlined in Figure 57. Data Sheet 248 2000-09-14 RSTA register (or last byte of received data) PEB 20532 PEF 20532 Programming Action taken by CPU Interrupt indication to CPU Reset Receiver (CMDRH.RRES) Activate Receiver (CCR3L.RAC) START WAIT FOR INTERRUPT 'RPF' Interrupt 'RME'/'TCD' Interrupt Read registers RBCL, RBCH (Rc Byte Count) Read [32]1) bytes from RFIFO Read [RBCL % 32]1), 2) bytes from RFIFO Release RFIFO (CMDRH.RMC) 1) A receive threshold of 32 bytes is the default for HDLC/PPP mode. It can be programmed with bit field RFTH(1:0) in register CCR3H. 2) The number of bytes stored in RFIFO can be determined by evaluating the lower bits in register RBCL (depending on the selected receive threshold RFTH(1:0)). Figure 57 Interrupt Driven Data Reception (Flow Diagram) Data Sheet 249 2000-09-14 PEB 20532 PEF 20532 Programming 6.3 External DMA Supported Mode The following table provides a definition of terms used in this chapter to describe the operation with external DMA controller support. Table 17 Packet DMA Terminology A "Packet" is a connected block of data bytes. This can be an HDLC/PPP frame as well as a number of ASYNC/ BISYNC characters up to a specific limit (received termination character, CMDRH:RFRD command). If a receive status byte (RSTA) is attached to data bytes, it is also considered as part of the packet. A "Buffer" is a limited space in memory that is reserved for DMA reception/transmission. SEROCCO-M can optionally keep track of predefined (receive) buffer limits and notify the CPU with an appropriate interrupt if this functionality is not provided by the external DMA controller. A packet can go into one single buffer, or it can go fragmented into multiple buffers. A "Block" is the amount of data that is transfered from the memory to the XFIFO (transmit DMA transfer) or from the RFIFO to the memory. In HDLC/PPP modes the block size is 32 bytes by default. It can be lowered with the receive FIFO threshold in register CCR3H, bit field 'RFTH(1..0)'. A "Bus Cycle" corresponds to a single byte/word transfer. Multiple bus cycles make up a block transfer. A "DMA Transfer" is the movement of complete buffers and/or packets between the XFIFO/RFIFO and the memory by the external DMA controller. Buffer Block Bus Cycle DMA Transfer 6.3.1 Data Transmission (With External DMA Support) Any packet transmission is prepared by initializing the external DMA controller with the transmit buffer start address and writing the packet size in number of bytes to registers XBCL/XBCH. Now there are two possible scenarios: * If the prepared transmit buffer in memory contains a complete packet, the start command for DMA transmission is issued by setting bits 'XF' and 'XME' in register XBCH to '1'. The DMA support logic will request the external DMA controller to transfer data into the XFIFO . After the last byte has been transmitted, the protocol machine appends the trailer (e.g. CRC and Flag in HDLC), if applicable. The Transmit DMA Transfer End (TDTE) interrupt is generated (refer to Figure 58). Data Sheet 250 2000-09-14 PEB 20532 PEF 20532 Programming * If a transmit packet is distributed over more than one transmit buffer in memory, the 'XF' command (without setting the 'XME' bit) forces SEROCCO-M to request data transfers from the external DMA controller from this buffer. A Transmit DMA Transfer End (TDTE) interrupt is generated whenever a block of CPU / MEMORY Packet n: (prepare external DMA controller with buffer base address) (write transmit byte count with command bit 'XF'+'XME') SEROCCO-M XBC TFIFO DMA transfer of ... TFIFO TFIFO TDTE interrupt ALLS interrupt (optional) Packet (n+1): (prepare external DMA controller with buffer base address) (write transmit byte count with command bit 'XF'+'XME') XBC ... Figure 58 DMA Transmit (Single Buffer per Packet) Data Sheet 251 2000-09-14 PEB 20532 PEF 20532 Programming CPU / MEMORY Packet n, Buffer 0: (prepare external DMA controller with buffer base address) (write transmit byte count with command bit 'XF') DMA transfer of SEROCCO-M XBC TFIFO ... TFIFO TFIFO TDTE interrupt Packet n, Buffer 1: (prepare external DMA controller with buffer base address) (write transmit byte count with command bit 'XF') DMA transfer of XBC TFIFO ... TFIFO TFIFO TDTE interrupt Packet n, Buffer m: (prepare external DMA controller with buffer base address) (write transmit byte count with command bit 'XF'+'XME') DMA transfer of XBC TFIFO ... TFIFO TFIFO TDTE interrupt ALLS interrupt (optional) Figure 59 Fragmented DMA Transmission (Multiple Buffers per Packet) Data Sheet 252 2000-09-14 PEB 20532 PEF 20532 Programming 6.3.2 Data Reception (With External DMA Support) The receive DMA support logic is able to limit its requesting for data transfers to a byte count programmed in register RMBSL/RMBSH. If the external DMA controller is capable of handling maximum receive buffer sizes itself, this feature can be disabled by setting bit RMBSH:DRMBS to '1'. If a new packet is received by the SCC, the DMA support logic will request the external DMA controller to move receive data out of the RFIFO. Now there are two possible scenarios: * If the maximum buffer size programmed in register RMBSL/RMBSH has been transferred (only if RMBSH:DRMBS = '0'), SEROCCO-M stops requesting for data transfers and a Receive Buffer Full (RBF) interrupt is generated. The CPU now updates the receive buffer base address in the external DMA controller and releases the receive DMA control logic by setting the 'RE' bit in register RMBSH. Optionally the maximum buffer size value can be updated with the same register write access. * If the end of a received packet/block is part of the curent DMA transfer, SEROCCOM generates a Receive DMA Transfer End (RDTE) interrupt and stops operation. The CPU now reads the received byte count from registers RBCL/RBCH. The receive DMA support logic will not continue requesting for data transfer until it is set up again with the 'RE' command in register RMBSH. If in packet oriented protocol modes (HDLC, PPP) the maximum receive buffer size RMBS is chosen to be larger than the expected receive packets, each buffer will contain the whole packet (see Figure 60). In this case (or if RMBSH:DRMBS = '1') a Receive Buffer Full (RBF) interrupt will never occur, simplifying the software. To ensure that no packets exceeding the maximum buffer size are forwarded from the SCC to the RFIFO, the receive packet length should be limited with registers RLCRL/RLCRH. Data Sheet 253 2000-09-14 PEB 20532 PEF 20532 Programming CPU / MEMORY SEROCCO-M Packet 0: (p re pare e xte rna l D M A co ntroller w ith re ceive bu ffe r start ad dress) (set m ax. receive bu ffer size and issu e 'R E ' co m m a nd) RM BS R F IF O D M A transfer of all re ceive da ta bytes ... R F IF O R F IF O R D T E inte rrup t (re ad R B C register) (is sue 'R M C ' com m a nd ) RBC CMDR Packet 1: (p rep are e xterna l D M A con tro ller w ith receive bu ffer start ad dre ss) ... Figure 60 DMA Receive (Single Buffer per Packet) Figure 61 shows an example for fragmented reception of a packet larger than the prepared receive buffers in memory. In this case the length of the received packet is 199 bytes, each of the buffers in host memory is 128 bytes deep: Data Sheet 254 2000-09-14 PEB 20532 PEF 20532 Programming 199 Bytes Payload Packet ... 32 32 32 32 32 32 7 ... Receive Buffers in Memory 1 1 128 1st packet fragment 128 2nd packet fragment Figure 61 Fragmented Reception per DMA (Example) After the external DMA controller is initialized with the base address of receive buffer #1 and the maximum buffer size RMBS is written to SEROCCO-M, simultaneously activated with the 'RE' command, requesting of DMA transfer from the RFIFO to the receive buffer takes place in blocks of 32 bytes (unless changed with bit field 'RFTH' in register CCR3H). After four 32-byte-blocks have been transferred, the first receive buffer is filled up completely with receive data. The SEROCCO-M indicates this by generating the RBF interrupt. Now the CPU has to provide the base address of the second receive buffer to the external DMA controller and issue the 'RE' command to SEROCCO-M again. This allows the external DMA controller to continue data transfers into the second receive buffer. After another two 32-byte-blocks have been transferred, the DMA request for the remaining 7 bytes (including the RSTA byte) is generated to the external DMA controller, follwed by the generation of the RDTE interrupt. Now the DMA transfer is completed and software has to read the number of received bytes from the Receive Byte Count registers RBCL/RBCH. The following figure (Figure 62) gives the sequence of actions from both, the SEROCCO-M and the CPU for this example (fragmented reception of 199 bytes into two receive buffers): Data Sheet 255 2000-09-14 PEB 20532 PEF 20532 Programming CPU / MEMORY Packet 1, Fragment 1: (p re pa re exte rn al D M A co ntrolle r w ith re ceive b uffe r s tart a ddress ) (se t m ax. re ceive bu ffe r s ize to 1 28 bytes an d issue 'R E ' com m a nd ) 32 D M A tra nsfe r of 1 28 rece ive data b yte s 32 32 32 SEROCCO-M RM BS R F IF O R F IF O R F IF O R F IF O R B F interrup t Packet 1, Fragment 2: (p re pa re exte rn al D M A co ntrolle r w ith re ceive b uffe r s tart a ddress ) (issu e 'R E ' c om m a nd ) RM BS 32 D M A tran sfer of 71 rece ive data b yte s 32 7 R F IF O R F IF O R F IF O R D T E interrup t (re ad R B C register) (iss ue 'R M C ' com m a nd ) RBC CMDR Packet 2, Fragment 1: (pre pa re extern al D M A controlle r w ith rece ive b uffer sta rt a dd re ss) ... Figure 62 Fragmented Reception Sequence (Example) Data Sheet 256 2000-09-14 PEB 20532 PEF 20532 Electrical Characteristics 7 7.1 Parameter Electrical Characteristics Absolute Maximum Ratings Symbol Limit Values 0 to 70 - 40 to 85 - 65 to 125 - 0.3 to 3.6 - 0.4 to 5.5 2000 Unit Ambient temperature under bias Storage temperature IC supply voltage PEB PEF Voltage on any signal pin with respect to ground ESD robustness1) HBM: 1.5 kW, 100 pF 1) TA TA Tstg VDD3 VS VESD,HBM C C C V V V According to MIL-Std 883D, method 3015.7 and ESD Ass. Standard EOS/ESD-5.1-1993. Note: Stresses above those listed here may cause permanent damage to the device. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 7.2 Parameter Operating Range Symbol 0 -40 0 3.0 0 Limit Values min. max. 70 85 125 3.6 0 Unit Test Condition Ambient temperature PEB TA PEF TA Junction temperature Supply voltage Ground C C C V V TJ VDD3 VSS Note: In the operating range, the functions given in the circuit description are fulfilled. Data Sheet 226 2000-09-14 PEB 20532 PEF 20532 Electrical Characteristics 7.3 Parameter DC Characteristics Symbol Limit Values min. max. 0.8 5.5 5.5 0.45 V V V V V 50 mA - 0.4 2.0 2.1 Unit Notes Input low voltage Input high voltage Output low voltage Output high voltage Power supply current operational (average) VIL VIH VOL VOH 2.4 ICC (AV) VDD = 3.3 V VDD = 3.6 V IOL = 7 mA 1) IOL = 2 mA 2) IOH = - 1.0 mA VDD = 3.3 V, TA = 25 C, CLK = 33 MHz, XTAL = 20 MHz, inputs at VSS/VDD, no output loads power down (no clocks) Power dissipation ICC (PD) P 0.01 150 mA VDD = 3.3 V, TA = 25 C mW VDD = 3.3 V, TA = 25 C, CLK = 33 MHz, XTAL = 20 MHz, inputs at VSS/VDD, no output loads Input leakage current ILI 1 mA VDD = 3.3 V, GND = 0 V; inputs at VSS/VDD, no output loads Output leakage current ILO 1 mA VDD = 3.3 V, GND = 0 V; VOUT = 0 V, VDDP + 0.4 1) 2) Apply to the next pins: TxDA, TxDB. Apply to all the I/O and O pins that do not appear in the list in note 1), except XTAL2. The listed characteristics are ensured over the operating range of the integrated circuit. Typical characteristics specify mean values expected over the production spread. If not otherwise specified, typical characteristics apply at TA = 25 C and the given supply voltage. Data Sheet 227 2000-09-14 PEB 20532 PEF 20532 Electrical Characteristics 7.4 AC Characteristics Interface Pins TA = 0 to + 70 C; VDD3 = 3.3 V 0.3 V Inputs are driven to 2.4 V for a logical "1" and to 0.4 V for a logical "0". Timing measurements are made at 2.0 V for a logical "1" and at 0.8 V for a logical "0". The AC testing input/output waveforms are shown below. 2.4 2.0 Test Points 0.8 0.45 0.8 2.0 Device Under Test C Load = 50 pF ITS09800 Figure 60 Input/Output Waveform for AC Tests 7.5 Capacitances Interface Pins Table 18 Capacitances TA = 25 C; VDD3 = 3.3 V 0.3 V, VSS = 0 V Symbol Limit Values min. max. 5 10 15 Parameter Input capacitance Output capacitance I/O-capacitance Unit pF pF pF Test Condition CIN COUT CIO Data Sheet 228 2000-09-14 PEB 20532 PEF 20532 Electrical Characteristics 7.6 Table 19 Parameter Thermal Package Characteristics Thermal Package Characteristics P-TQFP-100-3 Symbol Ambient Temperature: TA=-40C TA=+25C TA=+25C TA=+25C TA=+25C Value Unit Thermal Package Resistance Junction to Ambient Airflow: without airflow without airflow airflow 1 m/s (~200 lfpm) airflow 2 m/s (~400 lfpm) airflow 3 m/s (~600 lfpm) qJA(0,-40) qJA(0,25) qJA(1,25) qJA(2,25) qJA(3,25) 45.7 41.5 39.6 38.8 38.4 K/W K/W K/W K/W K/W Data Sheet 229 2000-09-14 PEB 20532 PEF 20532 Electrical Characteristics 7.7 7.7.1 7.7.1.1 Timing Diagrams Microprocessor Interface Timing Microprocessor Interface Clock Timing 1 2 3 CLK Figure 61 Table 20 Microprocessor Interface Clock Timing Microprocessor Interface Clock Timing Limit Values min. max. 30 0 11 11 Unit ns MHz ns ns No. Parameter 1 2 3 1) CLK clock period CLK frequency CLK high time CLK low time 33 A clock supply is needed for read access to the on-chip interrupt status registers (ISR, DISR) and for general purpose port (GPP) operation. Data Sheet 230 2000-09-14 PEB 20532 PEF 20532 Electrical Characteristics 7.7.1.2 Infineon/Intel Bus Interface Timing A(7:0) BHE1) 4 6 5 7 CS 8 17 RD 16 INT2) D(7:0) D(15:8)1) 14a 10 11 11a 14 15 15a READY (1) Signals BHE and D(15:8) only available in 16-bit Infineon/Intel bus mode. (2) Interrupt signal shown is push-pull, active high. Same timings apply to push-pull, active low interrupt signal. In case of open-drain output the timing depends on external components. Figure 62 A(7:0) BHE1) Infineon/Intel Read Cycle Timing 4 6 5 7 CS 9 17 WR 12 13 D(7:0) D(15:8)1) 14a 14 15 15a READY (1) Signals BHE and D(15:8) only available in 16-bit Infineon/Intel bus mode. Figure 63 Infineon/Intel Write Cycle Timing Data Sheet 231 2000-09-14 PEB 20532 PEF 20532 Electrical Characteristics CS 1) DACK RD last read access to RFIFO 18 DRR (1) During DMA cycles, FIFO is selected with the corresponding FIFO address plus CS asserted, or with DACK asserted. Figure 64 CS 1) DACK WR Infineon/Intel DMA Read Cycle Timing last write access to XFIFO 19 DRT (1) During DMA cycles, FIFO is selected with the corresponding FIFO address plus CS asserted, or with DACK asserted. Figure 65 Infineon/Intel DMA Write Cycle Timing A(7:0) BHE1) 20 21 ALE 22 23 WR RD (1) Signal BHE only available in 16-bit Infineon/Intel bus mode Figure 66 Infineon/Intel Multiplexed Address Timing Data Sheet 232 2000-09-14 PEB 20532 PEF 20532 Electrical Characteristics Table 21 Infineon/Intel Bus Interface Timing Limit Values min. 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 1) No. Parameter active address to active RD/WR setup time inactive RD/WR to inactive address hold time active CS to active RD/WR setup time inactive RD/WR to inactive CS hold time RD active pulse width WR active pulse width active RD to valid data delay inactive RD to invalid data hold time valid data to inactive WR setup time inactive WR to invalid data hold time active RD/WR to active READY delay inactive RD/WR to inactive READY delay inactive RD to inactive INT/INT delay RD/WR inactive pulse width active RD to inactive DRR delay active WR to inactive DRT delay active address to inactive ALE setup time inactive ALE to inactive address hold time ALE pulse width inactive ALE to active RD/WR setup time 30 22 22 5 5 30 0 5 8 0 2 0 301) 30 Unit ns ns ns ns ns ns max. 20 25 6 5 20 20 15 15 1 ns ns ns ns ns ns ns ns ns TCLK2) ns ns ns ns ns ns ns 11a inactive RD to data high impedance delay 14a active CS to driven READY delay 15a inactive CS to READY high impedance delay At least one rising CLK edge must appear during read pulse active for interrupt status register (ISR, DISR) read. TCLK is the system clock (CLK) period. 2) Data Sheet 233 2000-09-14 PEB 20532 PEF 20532 Electrical Characteristics 7.7.1.3 Motorola Bus Interface Timing 40 41 A(7:0) A(7:1)1) CS 42 43 R/W DS LDS, UDS1) 44 46 45 55 54 INT2) D(7:0) D(15:8)1) 52a 48 49 49a 52 53 53a DTACK (1) Signals LDS, UDS and D(15:8) only available in 16-bit Motorola bus mode (2) Interrupt signal shown is push-pull, active high. Same timings apply to push-pull, active low interrupt signal. In case of open-drain output the timing depends on external components. Figure 67 A(7:0) A(7:1)1) Motorola Read Cycle Timing 40 41 CS 42 44 43 45 R/W 47 55 DS LDS, UDS1) 50 51 D(7:0) D(15:8)1) 52a 52 53 53a DTACK (1) Signals LDS, UDS and D(15:8) only available in 16-bit Motorola bus mode Figure 68 Data Sheet Motorola Write Cycle Timing 234 2000-09-14 PEB 20532 PEF 20532 Electrical Characteristics CS 1) DACK R/W last read access to RFIFO 56 DS DRR (1) During DMA cycles, FIFO is selected with the corresponding FIFO address plus CS asserted, or with DACK asserted. Figure 69 Motorola DMA Read Cycle Timing CS 1) DACK R/W last write access to XFIFO 57 DS DRT (1) During DMA cycles, FIFO is selected with the corresponding FIFO address plus CS asserted, or with DACK asserted. Figure 70 Table 22 Motorola DMA Write Cycle Timing Motorola Bus Interface Timing Limit Values min. max. ns ns ns ns ns ns 1) No. Parameter 40 41 42 43 44 45 46 active address to active DS setup time inactive DS to inactive address hold time active CS to active DS setup time inactive DS to inactive CS hold time active R/W to active DS setup time inactive DS to inactive R/W hold time DS active pulse width (read access) 0 0 0 0 0 0 30 Unit ns Data Sheet 235 2000-09-14 PEB 20532 PEF 20532 Electrical Characteristics Table 22 Motorola Bus Interface Timing (cont'd) Limit Values min. 47 48 49 50 51 52 53 54 55 56 57 1) No. Parameter DS active pulse width (write access) active DS (read) to valid data delay inactive DS (read) to invalid data hold time valid data to inactive DS (write) setup time inactive DS (write) to invalid data hold time active DS to active DTACK delay inactive DS to inactive DTACK delay inactive DS (read) to inactive INT/INT delay DS inactive pulse width active DS (read) to inactive DRR delay active DS (write) to inactive DRT delay 30 22 22 5 30 Unit ns max. 20 20 ns ns ns ns ns 20 20 15 15 1 ns ns ns ns TCLK ns ns ns 49a inactive DS (read) to data high impedance delay 10 10 52a active CS to driving DTACK delay 53a inactive CS to DTACK high impedance delay At least one rising CLK edge must appear during read data strobe active for interrupt status register (ISR, DISR) read. Data Sheet 236 2000-09-14 PEB 20532 PEF 20532 Electrical Characteristics 7.7.2 7.7.2.1 PCM Serial Interface Timing Clock Input Timing 81,84,87 RxCLK TxCLK XTAL1 Figure 71 Table 23 82,85,88 83,86,89 Clock Input Timing Clock Input Timing Limit Values min. max. 62 25 25 62 25 25 25 25 12 12 12 12 Unit ns ns ns ns ns ns ns ns ns ns ns ns No. Parameter 81 82 83 84 85 86 87 88 89 RxCLK clock period RxCLK high time RxCLK low time TxCLK clock period TxCLK high time TxCLK low time XTAL1 clock period (internal oscillator used) XTAL1 clock period (TTL clock signal supplied) XTAL1 high time (internal oscillator used) XTAL1 high time (TTL clock signal supplied) XTAL1 low time (internal oscillator used) XTAL1 low time (TTL clock signal supplied) 100 46 46 Data Sheet 237 2000-09-14 PEB 20532 PEF 20532 Electrical Characteristics 7.7.2.2 Receive Cycle Timing 90 Receive Clock (Note 1) 91 92 RxD (Note 2) 91 92 91 92 RxD (Note 3) 93 94 CD (Note 4) (1) Whichever supplies the receive clock depending on the selected clock mode: externally clocked via RxCLK or XTAL1 or internally clocked via DPLL, BCR or BRG. (No edge relation can be measured if the internal receive clock is derived from the external clock source by division stages (BRG, BCR) or DPLL) (2) NRZ, NRZI and Manchester data encoding (3) FM0 and FM1 data encoding (4) If Carrier Detect auto start feature enabled (not for clock modes 1, 4 and 5) Figure 72 Table 24 Receive Cycle Timing Receive Cycle Timing No. Parameter Receive data rates externally clocked (HDLC) internally clocked (DPLL modes) internally clocked (non DPLL modes) 90 Clock period externally clocked internally clocked (DPLL modes) internally clocked (non DPLL modes) 91 92 RxD to RxCLK setup time RxD to RxCLK hold time 0 0 0 62 Limit Values min. max. 16 2 16 Unit Mbit/s Mbit/s Mbit/s ns ns ns ns ns 480 62 5 5 Data Sheet 238 2000-09-14 PEB 20532 PEF 20532 Electrical Characteristics Table 24 Receive Cycle Timing (cont'd) No. Parameter 93 94 CD to RxCLK rising edge setup time CD to RxCLK falling edge hold time 5 5 Limit Values min. max. Unit ns ns 7.7.2.3 Transmit Cycle Timing 100 Transmit Clock (Note1) 101 TxD (Note2,5) 102 102 TxD (Note3) 103 103 TxCLK (Note4) 104 105 CxD CTS 106 106 RTS (Note5) (1) Whichever supplies the transmit clock depending on the selected clock mode: externally clocked via TxCLK, RxCLK or XTAL1 or internally clocked via DPLL, BCR or BRG. (No edge relation can be measured if the internal transmit clock is derived from the external clock source by division stages (BRG, BCR) or DPLL) (2) NRZ, NRZI and Manchester data encoding (3) FM0 and FM1 data encoding (4) If TxCLK output feature is enabled (only in some clock modes) (5) The timing is valid for non bus configuration modes and bus configuration mode 1. In bus configuration mode 2, TxD and RTS are right shifted for 0.5 TxCLK periods i.e. driven by the falling TxCLK edge. Figure 73 Transmit Cycle Timing Data Sheet 239 2000-09-14 PEB 20532 PEF 20532 Electrical Characteristics Table 25 Transmit Cycle Timing Limit Values min. Transmit data rates externally clocked internally clocked (DPLL modes) internally clocked (non DPLL modes) 100 Clock period externally clocked internally clocked (DPLL modes) internally clocked (non DPLL modes) 101 TxD to TxCLK delay (NRZ, NRZI encoding) 102 TxD to TxCLK delay (FM0, FM1, Manchester encoding) 103 TxD to TxCLK(out) delay (output function enabled) 10 104 CxD to TxCLK setup time CTS to TxCLK setup time 105 CxD to TxCLK hold time CTS to TxCLK hold time 106 RTS to TxCLK delay (not bus configuration mode) RTS to TxCLK delay (bus configuration mode) 5 5 5 5 20 20 0 0 0 62 480 62 max. 16 2 16 Mbit/s Mbit/s Mbit/s ns ns ns ns ns ns ns ns ns ns ns ns Unit No. Parameter 25 25 25 Data Sheet 240 2000-09-14 PEB 20532 PEF 20532 Electrical Characteristics 7.7.2.4 Clock Mode 1 Strobe Timing RxCLK 110 111 CD (RxStrobe) RxD (Note1) valid 112 113 TxCLK (TxStrobe) 114 115 TxD (Note1,3) 114 115 TxD (Note2,3) (1) No bus configuration mode and bus configuration mode 1 (2) Bus configuration mode 2 (3) TxD Idle is either active high or high impedance if 'open drain' output type is selected. Figure 74 Table 26 Clock Mode 1 Strobe Timing Clock Mode 1 Strobe Timing Limit Values min. max. ns ns ns ns 25 25 ns ns 5 5 5 5 10 10 No. Parameter 110 Receive strobe to RxCLK setup 111 Receive strobe to RxCLK hold 112 Transmit strobe to RxCLK setup 113 Transmit strobe to RxCLK hold 114 TxD to RxCLK delay 115 TxD to RxCLK high impedance delay Unit Data Sheet 241 2000-09-14 PEB 20532 PEF 20532 Electrical Characteristics 7.7.2.5 Clock Mode 4 Gating Timing 141 RxCLK 140 RCG 142 RxD 143 Figure 75 Clock Mode 4 Receive Gating Timing 146 TxCLK 145 TCG 147 TxD Figure 76 Table 27 Clock Mode 4 Transmit Gating Timing Clock Mode 4 Gating Timing No. Parameter min. 140 RCG setup time 141 RCG hold time 142 RxD setup time 143 RxD hold time 145 TCG setup time 146 TCG hold time 147 TxCLK to TxD delay1) 1) Limit Values max. 5 5 5 5 0 6 10 25 Unit ns ns ns ns ns ns ns Note that the TxD output is delayed for one additional clock with respect to the gating signal TCG! Data Sheet 242 2000-09-14 PEB 20532 PEF 20532 Electrical Characteristics 7.7.2.6 Clock Mode 5 Frame Synchronisation Timing RxCLK 130 131 CD (FSC) 132 132 TxCLK Note1 132 132 TxCLK Note2 (1) Normal operation and bus configuration mode 1 (2) Bus configuration mode 2 Figure 77 Table 28 Clock Mode 5 Frame Synchronisation Timing Clock Mode 5 Frame Synchronisation Timing No. Parameter min. 130 Sync pulse to RxCLK setup time 131 Sync pulse to RxCLK hold time 132 TxCLKout to RxCLK delay (time slot monitor) 10 0 10 Limit Values max. Unit ns ns 27 ns Data Sheet 243 2000-09-14 PEB 20532 PEF 20532 Electrical Characteristics 7.7.3 Reset Timing power-on VDD3 151 CLK 150 RESET Figure 78 Table 29 Reset Timing Reset Timing No. 150 151 Parameter min. RESET pulse width Number of CLK cycles after RESET inactive 500 2 Limit Values max. Unit ns CLK cycles Note: RESET may be asserted and deasserted asynchronous to CLK at any time. Data Sheet 244 2000-09-14 PEB 20532 PEF 20532 Electrical Characteristics 7.7.4 JTAG-Boundary Scan Timing TRST 160 161 162 TCK 163 164 TMS 165 166 TDI 167 TDO Figure 79 Table 30 JTAG-Boundary Scan Timing JTAG-Boundary Scan Timing No. Parameter min. 160 TCK period 161 TCK high time 162 TCK low time 163 TMS setup time 164 TMS hold time 165 TDI setup time 166 TDI hold time 167 TDO valid delay 166 80 80 30 10 30 20 Limit Values max. Unit ns ns ns ns ns ns ns 60 ns Data Sheet 245 2000-09-14 PEB 20532 PEF 20532 Test Modes 8 8.1 Test Modes JTAG Boundary Scan Interface In the SEROCCO-M a Test Access Port (TAP) controller is implemented. The essential part of the TAP is a finite state machine (16 states) controlling the different operational modes of the boundary scan. Both, TAP controller and boundary scan, meet the requirements given by the JTAG standard: IEEE 1149.1. Figure 83 gives an overview about the TAP controller. Test Access Port (TAP) TCK CLOCK Pins CLOCK TRST Reset BS Data IN Clock Generation 1 2 Identification Scan (32 bit) . . . TMS Test Control TAP Controller Control Bus - Finite State Machine - Instruction Register (3 bit) - Test Signal Generator 6 ID Data out SS Data out Boundary Scan (n bit) n TDI Data in . . . TDO Enable Data out Figure 83 Block Diagram of Test Access Port and Boundary Scan Unit If no boundary scan operation is planned TRST has to be connected with VSS. TMS, TCK and TDI do not need to be connected since pull-up transistors ensure high input levels in this case. Nevertheless it would be a good practice to put these unused inputs to defined levels, using pull-up resistors. Test handling (boundary scan operation) is performed via the pins TCK (Test Clock), TMS (Test Mode Select), TDI (Test Data Input) and TDO (Test Data Output) when the TAP controller is not in its reset state, i.e. TRST is connected to VDD or it remains unconnected due to its internal pull-up. Test data at TDI are loaded with a 4-MHz clock Data Sheet 277 2000-09-14 PEB 20532 PEF 20532 Test Modes signal connected to TCK. `1' or `0' on TMS causes a transition from one controller state to another; constant '1' on TMS leads to normal operation of the chip. Table 31 Boundary Scan Sequence of SEROCCO-M Seq. No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 Pin TDI -> CTSB CTSA CDA RxDA RxCLKA TxDA TxCLKA RTSA RESET INT GP10 GP9 GP8 internal GP6 internal internal internal A7 A6 A5 A4 A3 A2 A1 A0 I/O Number of Boundary Scan Cells 1 1 1 1 1 2 3 Constant Value In, Out, Enable 0 0 1 0 0 00 000 0 0 01 011 110 000 010 000 001 100 000 000 000 000 000 000 000 000 000 I I I I I O I O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O 1 1 2 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 278 Data Sheet 2000-09-14 PEB 20532 PEF 20532 Test Modes Table 31 Boundary Scan Sequence of SEROCCO-M Seq. No. 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 Pin BM/ALE CS BHE W/R internal internal internal internal internal internal internal internal RD WR READY CLK D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 I/O I I I/O I/O O O O O O O O O I/O I/O I/O I I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O Number of Boundary Scan Cells 1 1 3 3 2 2 2 2 2 2 2 2 3 3 3 1 2 2 2 2 2 2 2 3 2 2 2 2 2 2 279 Constant Value In, Out, Enable 0 0 000 000 00 00 00 00 00 00 00 00 000 000 000 0 00 00 00 00 00 00 00 000 00 00 00 00 00 00 2000-09-14 Data Sheet PEB 20532 PEF 20532 Test Modes Table 31 Boundary Scan Sequence of SEROCCO-M Seq. No. 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 Pin D14 D15 DRTA DACKA DRRA DRRB DRTB DACKB RTSB RxDB RxCLKB TxDB TxCLKB CDB ADS I/O I/O I/O I/O I I/O I/O I/O I/O O I I O I/O I O Number of Boundary Scan Cells 2 3 3 1 3 3 3 3 1 1 1 2 3 1 2 Constant Value In, Out, Enable 00 000 000 0 000 000 000 000 0 0 0 00 000 0 00 -> TDO An input pin (I) uses one boundary scan cell (data in), an output pin (O) uses two cells (data out, enable) and an I/O-pin (I/O) uses three cells (data in, data out, enable). Note that some functional output and input pins of SEROCCO-M are tested as I/O pins in boundary scan, hence using three cells. The boundary scan unit of SEROCCO-M contains a total of n = 158 scan cells. The right column of Table 31 gives the initialization values of the cells. The desired test mode is selected by serially loading a 3-bit instruction code into the instruction register via TDI (LSB first); see Table 32. Data Sheet 280 2000-09-14 PEB 20532 PEF 20532 Test Modes Table 32 Boundary Scan Test Modes Instruction (Bit 2 ... 0) 000 001 010 011 111 others Test Mode EXTEST (external testing) INTEST (internal testing) SAMPLE/PRELOAD (snap-shot testing) IDCODE (reading ID code) BYPASS (bypass operation) handled like BYPASS EXTEST is used to examine the interconnection of the devices on the board. In this test mode at first all input pins capture the current level on the corresponding external interconnection line, whereas all output pins are held at constant values (`0' or `1', according to Table 31). Then the contents of the boundary scan is shifted to TDO. At the same time the next scan vector is loaded from TDI. Subsequently all output pins are updated according to the new boundary scan contents and all input pins again capture the current external level afterwards, and so on. INTEST supports internal testing of the chip, i.e. the output pins capture the current level on the corresponding internal line whereas all input pins are held on constant values (`0' or `1', according to Table 31). The resulting boundary scan vector is shifted to TDO. The next test vector is serially loaded via TDI. Then all input pins are updated for the following test cycle. Note: In capture IR-state the code `001' is automatically loaded into the instruction register, i.e. if INTEST is wanted the shift IR-state does not need to be passed. SAMPLE/PRELOAD is a test mode which provides a snap-shot of pin levels during normal operation. IDCODE: A 32-bit identification register is serially read out via TDO. It contains the version number (4 bits), the device code (16 bits) and the manufacturer code (11 bits). The LSB is fixed to `1'. TDI -> 0010 0000 0000 0101 1110 0000 1000 001 1 -> TDO Note: Since in test logic reset state the code `011' is automatically loaded into the instruction register, the ID code can easily be read out in shift DR state which is reached by TMS = 0, 1, 0, 0. BYPASS: A bit entering TDI is shifted to TDO after one TCK clock cycle. Data Sheet 281 2000-09-14 PEB 20532 PEF 20532 Package Outlines 9 Package Outlines P-TQFP-100-3 (Plastic Thin Quad Flat Package) Sorts of Packing Package outlines for tubes, trays etc. are contained in our Data Book "Package Information". Dimensions in mm Data Sheet 282 2000-09-14 GPP09189 |
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